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(parent: e46ebc2) | patch
new PLL with 50 MHz output
authorJan Michel <j.michel@gsi.de>
Sun, 25 Aug 2013 14:02:07 +0000 (16:02 +0200)
committerJan Michel <j.michel@gsi.de>
Sun, 25 Aug 2013 14:02:07 +0000 (16:02 +0200)
commita5b662e512bad594de7a0ef1b96ead8dec78e5a9
tree361298797bf7ad6b954a473fc3a9f15f798c48d5tree | snapshot
parente46ebc2ecf4fdc6503b8742c94ad502572e6e1d9commit | diff
new PLL with 50 MHz output
base/cores/pll_in200_out100_50.ipx [new file with mode: 0644] blob
base/cores/pll_in200_out100_50.lpc [new file with mode: 0644] blob
base/cores/pll_in200_out100_50.vhd [new file with mode: 0644] blob
TRB3 VHDL