]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/commit
Dirich update: input clock 200 MHz, flash connected to clock signal
authorJan Michel <j.michel@gsi.de>
Fri, 18 Mar 2016 15:44:03 +0000 (16:44 +0100)
committerJan Michel <j.michel@gsi.de>
Fri, 18 Mar 2016 15:44:03 +0000 (16:44 +0100)
commitad732cb13534fc94955435529ccdea8f305ffa02
treec4b4033e9817a1a0d587c9e2846e8f837f830c3d
parent67a020742e249f2ef3b896d999ce478c384afdc6
Dirich update: input clock 200 MHz, flash connected to clock signal
code/clock_reset_handler.vhd
cores/pll_240_100/pll_240_100.lpc
cores/pll_240_100/pll_240_100.vhd
dirich/dirich.lpf
dirich/dirich.vhd