jspc29.x-matter.uni-frankfurt.de Git

]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commit

author	Jan Michel <j.michel@gsi.de>
	Tue, 10 Jul 2018 12:18:14 +0000 (14:18 +0200)
committer	Jan Michel <j.michel@gsi.de>
	Tue, 10 Jul 2018 12:18:14 +0000 (14:18 +0200)
commit	b526739dc28225b64df4907893506954b33b58eb
tree	132bc01c0911340057b270d9316d9fd08d9c8a98	tree \| snapshot
parent	e152ddf336bee411b86a54d20b34683adfec37c1	commit \| diff

change ring buffer almost full handling - now single words are discarded

27 files changed:

base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/generate_core.tcl		diff \| blob \| history
base/cores/ecp3/FIFO/generate_ngd.tcl		diff \| blob \| history
base/cores/ecp3/FIFO/msg_file.log		diff \| blob \| history
base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.cst		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.edn		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.jhd		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.lpc		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngd		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngo		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.srp		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_generate.log		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_core.tcl		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_ngd.tcl		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/msg_file.log		diff \| blob \| history
base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd		diff \| blob \| history
releases/tdc_v2.3/Channel_200.vhd		diff \| blob \| history

The FPGA-TDC files

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