jspc29.x-matter.uni-frankfurt.de Git

]> jspc29.x-matter.uni-frankfurt.de Git - cri.git/commit

author	Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
	Thu, 25 Feb 2021 09:33:03 +0000 (10:33 +0100)
committer	Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
	Thu, 25 Feb 2021 09:49:12 +0000 (10:49 +0100)
commit	b8f7354e03984a9dd55bab064f017107b9e14168
tree	fa3fd41530ecc169137c92fd34038fb96d8ff874	tree \| snapshot
parent	8b4eaa0aff86d7acc39b14bf32d0a2c0532c65a7	commit \| diff

hub_test: Replace TX buf bypass with phase aligner

This achieves a deterministic phase of the downlink TX data with respect
to the reference clock (and system/CBM clock).

hub_test/constrs/debug.xdc		diff \| blob \| history
hub_test/constrs/debug_tx_phase_aligner.xdc	[new file with mode: 0644]	blob
hub_test/constrs/hub_test.xdc		diff \| blob \| history
hub_test/hub_test.xpr		diff \| blob \| history
hub_test/src/hub_test.vhd		diff \| blob \| history

VHDL modules for TrbNet on CBM Xilinx hardware

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