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(parent: cf216cb) | patch
Ready for first test
authorhadeshyp <hadeshyp>
Fri, 26 Aug 2011 08:39:47 +0000 (08:39 +0000)
committerhadeshyp <hadeshyp>
Fri, 26 Aug 2011 08:39:47 +0000 (08:39 +0000)
commitc79a3a6859dbdc000f3920b7b99ce5caa77ee2e5
tree2a3d62ed1789cbb0537692c8bdadaba90986f157tree | snapshot
parentcf216cb32d82fdd5d62644ba6474a34fc912a59ccommit | diff
Ready for first test
base/trb3.xcf [new file with mode: 0644] blob
fpgatest/projects/trb3_central.pty [new file with mode: 0644] blob
fpgatest/projects/trb3_periph.ldf [new file with mode: 0644] blob
fpgatest/projects/trb3_periph.pty [new file with mode: 0644] blob
TRB3 VHDL