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(parent: 3d0a302) | patch
med_sync_control: Fix signal_sync source clocks
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Wed, 30 Sep 2020 13:17:13 +0000 (15:17 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Wed, 30 Sep 2020 16:35:20 +0000 (18:35 +0200)
commitc96a0e0116b435acecd93661eaadda13f984d807
tree9ec8ba10705a4c17183d7fd9be7a41fddb4c529ctree | snapshot
parent3d0a3028d9d7c8e605d5d79eebc4cfaac3dbe099commit | diff
med_sync_control: Fix signal_sync source clocks

The signal_sync instances for the finished_reset_* signals from
tx_reset_fsm and rx_reset_fsm had the source clock set to CLK_SYS, but
both source signals are synchronous to CLK_REF.
media_interfaces/sync/med_sync_control.vhd diff | blob | history
TrbNet VHDL code