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Add project endpoint_test
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Wed, 8 Jul 2020 15:59:32 +0000 (17:59 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Wed, 8 Jul 2020 15:59:32 +0000 (17:59 +0200)
commitcc5d97253dc16a735458790bbab554f14713bd76
tree3c858ce8e0be90210e1aa2df7c0e9fdf4f530296tree | snapshot
Add project endpoint_test

Migrated from the CBM RICH CRI test repo:

git.cbm.gsi.de/rich/rich_cri

Original code by: Adrian Weber <a.weber@gsi.de>
15 files changed:
endpoint_test/.gitignore [new file with mode: 0644] blob
endpoint_test/constrs/constr.xdc [new file with mode: 0644] blob
endpoint_test/constrs/debug.xdc [new file with mode: 0644] blob
endpoint_test/constrs/test.xdc [new file with mode: 0644] blob
endpoint_test/endpoint_test.xpr [new file with mode: 0644] blob
endpoint_test/ip/vio_0/vio_0.xci [new file with mode: 0644] blob
endpoint_test/ip/vio_0/vio_0.xml [new file with mode: 0644] blob
endpoint_test/scripts/compile.sh [new file with mode: 0755] blob
endpoint_test/scripts/generate_bitstream.tcl [new file with mode: 0644] blob
endpoint_test/sim/testbench_endpoint_hades_full_handler.vhd [new file with mode: 0644] blob
endpoint_test/sim/testbench_read_dna_address.vhd [new file with mode: 0644] blob
endpoint_test/sim/testbench_rx_control.vhd [new file with mode: 0644] blob
endpoint_test/src/config.vhd [new file with mode: 0644] blob
endpoint_test/src/endpoint_test.vhd [new file with mode: 0644] blob
endpoint_test/src/version.vhd [new file with mode: 0644] blob
VHDL modules for TrbNet on CBM Xilinx hardware