]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commit
Synplify: Set clock timing for ADC to 163MHz, enable retiming and pipelining
authorAndreas Neiser <neiser@kph.uni-mainz.de>
Wed, 11 Feb 2015 09:37:26 +0000 (10:37 +0100)
committerAndreas Neiser <neiser@kph.uni-mainz.de>
Sat, 13 Jun 2015 15:36:55 +0000 (17:36 +0200)
commitd2b64a1d660b8349045f83c7408cd626cbba6ebb
treec812fe752bdb7fae60bf79df506099507f2bccf5
parentf9b19485f5b29dddee3ba6bad254d734a8320ef0
Synplify: Set clock timing for ADC to 163MHz, enable retiming and pipelining
ADC/trb3_periph_adc.prj
ADC/trb3_periph_adc.sdc