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Initial revision
authorhadeshyp <hadeshyp>
Fri, 2 Feb 2007 10:49:22 +0000 (10:49 +0000)
committerhadeshyp <hadeshyp>
Fri, 2 Feb 2007 10:49:22 +0000 (10:49 +0000)
commitd4251d6e5566fe387aefbe0d108e6f0c2713b538
tree73c483ad01ae0179d987c24df577170bd8c1da89tree | snapshot
Initial revision
19 files changed:
compile2a.pl [new file with mode: 0755] blob
dsp_interface.vhd [new file with mode: 0644] blob
etrax_interface.vhd [new file with mode: 0755] blob
f_divider.vhd [new file with mode: 0644] blob
impact_batch_a.txt [new file with mode: 0644] blob
lvl1_and_lvl2_busy.vhd [new file with mode: 0755] blob
simpleupcounter_10bit.vhd [new file with mode: 0644] blob
simpleupcounter_16bit.vhd [new file with mode: 0644] blob
tdc_interface.vhd [new file with mode: 0755] blob
trb_v2a_fpga.ucf [new file with mode: 0644] blob
trb_v2a_fpga.vhd [new file with mode: 0644] blob
trb_v2a_fpga_syn.prj [new file with mode: 0644] blob
trb_v2a_fpga_syn.sdc [new file with mode: 0644] blob
trb_v2a_fpga_tb.vhd [new file with mode: 0644] blob
trigger_logic.vhd [new file with mode: 0755] blob
up_counter_17bit.vhd [new file with mode: 0644] blob
up_down_counter.vhd [new file with mode: 0644] blob
up_down_counter_10bit.vhd [new file with mode: 0644] blob
up_down_counter_16_bit.vhd [new file with mode: 0644] blob
TRB2 TDC readout designs