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(parent: e37a976) | patch
Added trb_net16_med_16_IC.vhd for Xilinix to the xilinx/ directory.
authorhadeshyp <hadeshyp>
Tue, 12 Oct 2010 13:52:56 +0000 (13:52 +0000)
committerhadeshyp <hadeshyp>
Tue, 12 Oct 2010 13:52:56 +0000 (13:52 +0000)
commitd440d0be7f5ee84662c04db7e604ad41af280b3e
tree0a5bbd6d1a58769f1049fe66fa7fd8ee6f1e83f0tree | snapshot
parente37a9768fbe1c003708d3604c53980b64885474fcommit | diff
Added trb_net16_med_16_IC.vhd for Xilinix to the xilinx/ directory.
This entity uses a Virtex4 output buffer ODDR to provide the clock signal
to the external entity.

Boris
xilinx/trb_net16_med_16_IC.vhd [new file with mode: 0644] blob
TrbNet VHDL code