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(parent: 96d60e9) | patch
The status registers are moved to the bus address 0xc100. Also debug registers (encod...
authorhadaq <hadaq>
Thu, 15 Nov 2012 11:40:44 +0000 (11:40 +0000)
committerhadaq <hadaq>
Thu, 15 Nov 2012 11:40:44 +0000 (11:40 +0000)
commitdf83d3c4a2d83375ef80dbdee916f49c6ea1ca33
tree44159a570a5ed085d721841fd3633559b8764871tree | snapshot
parent96d60e91bd9692f2f84aa6d75b42d587dde8851fcommit | diff
The status registers are moved to the bus address 0xc100. Also debug registers (encoder start, fifo write, lost hits) are included in the bus - 0xc200 0xc300 0xc400
19 files changed:
tdc_releases/tdc_v1.1.1/Adder_304.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/BusHandler.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Channel_200.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Readout.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Reference_Channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/TDC.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/bit_sync.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/trb3_periph.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/trb3_periph_constraints.lpf [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/trb3_periph_constraints.lpf.jan [new file with mode: 0644] blob
tdc_releases/tdc_v1.1.1/up_counter.vhd [new file with mode: 0644] blob
TRB3 VHDL