]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commit
re-add PLL to calibration signal generation
authorJan Michel <j.michel@gsi.de>
Wed, 7 Mar 2018 12:58:21 +0000 (13:58 +0100)
committerJan Michel <j.michel@gsi.de>
Wed, 7 Mar 2018 12:58:21 +0000 (13:58 +0100)
commite69691286f21f8e7ad1be6a9f9a41f5dbf934303
tree377ec503b6c3ff14b2270ea25a721b6e429619e8
parent527026dc9bef6315278ce192bb10b243684f9d0c
re-add PLL to calibration signal generation
releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
releases/tdc_v2.3/trb3_periph_gpin.vhd
releases/tdc_v2.3/trb3_periph_padiwa.vhd