Back a few steps. This is compiled including:

Back a few steps. This is compiled including:
- several syn_keep and syn_preserve attributes to keep signal names transparent
- synthesis constraints to get more control of clock resources.

This version has BOTH transmit and receive buffers and is therefore not synchronous.
However: The source-transmiter is clocked from the GPLL.
			The client-receiver is clocked from rx_full (as it should be)
			The client-transmiter is clocked from rx_full (max synch. with receiver)
			The source-receiver is also clocked with (source-)rx_full.

This seems to work ok. Next step is to remove the rx_fifo.
As rxiclk_ch0 is clocked with rx_full aswell, this should not make any difference.
Will try first for the source, second for the client aswell.

This should then be really synchronous, as Lattice claims that the TX-fifo has a fixed latency.

Seeing is believing.