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(parent: 5a995bb) | patch
Derive system clock from downlink reference clock
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Mon, 12 Oct 2020 10:39:20 +0000 (12:39 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Mon, 12 Oct 2020 10:39:20 +0000 (12:39 +0200)
commiteca4d17ef46fe9eeca90b0180856ca5002705f8e
tree8a33985b3be9f8661a15072b43528c8e83b2f5b9tree | snapshot
parent5a995bb2049b005b0cfad6952ab1782d7eded933commit | diff
Derive system clock from downlink reference clock

This gets rid of the separate fabric clock input port and prevents
timing errors stemming from the separate clock sources.
hub_test/constrs/hub_test.xdc diff | blob | history
hub_test/ip/clk_wiz_0/clk_wiz_0.xci diff | blob | history
hub_test/ip/clk_wiz_0/clk_wiz_0.xml diff | blob | history
hub_test/src/hub_test.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware