jspc29.x-matter.uni-frankfurt.de Git

]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commit

Add files from Cahit, compiles for Dirich

The FPGA-TDC files

base/cores/ecp5/TDC/Adder_288/Adder_288.vhd	[new file with mode: 0644]	blob
releases/tdc_v2.3/Channel_200.vhd		diff \| blob \| history
releases/tdc_v2.3/Encoder_288_Bit.vhd		diff \| blob \| history
releases/tdc_v2.3/ROM_encoder_ecp5.vhd		diff \| blob \| history
releases/tdc_v2.3/TDC_record.vhd		diff \| blob \| history
releases/tdc_v2.3/dirich_tdc_constraints.lpf		diff \| blob \| history
releases/tdc_v2.3/dirich_trbnet_constraints.lpf		diff \| blob \| history
releases/tdc_v2.3/rom_encoder/ecp5/ROM_encoder_3/ROM_encoder_3.vhd		diff \| blob \| history
releases/tdc_v2.3/tdc_components.vhd		diff \| blob \| history
releases/tdc_v2.3/unimportant_lines_constraints.lpf		diff \| blob \| history