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(parent: 181e248) | patch
Add signals for unused hub data ports
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Mon, 24 Aug 2020 13:03:12 +0000 (15:03 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Mon, 24 Aug 2020 13:03:12 +0000 (15:03 +0200)
commitee43a08c8ff16d8ec9e1415d54c149fadd2fd715
treebbbc0e73966493fd4f7fcd0bf9414afe0d43b41ctree | snapshot
parent181e24870b84107b358e0b750692e43801aa07d5commit | diff
Add signals for unused hub data ports

These are necessary to prevent "missing port association" errors during
synthesis with Vivado.
src/hub/trb_net16_cri_hub.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware