]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commit
new PLL for 240MHz -> 50MHz. Used for calibration Clock on combiner board of CBM...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 12 Jan 2021 16:17:59 +0000 (17:17 +0100)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 12 Jan 2021 16:17:59 +0000 (17:17 +0100)
commitf37a7a69a36dc0ad2addbab0c806a8f947edbcd3
tree5ad39a1cf5f6889afaf6ac3e5f3da520200b54df
parent83d55bb65d459817fcfc0d9f09d83540a00aa7cb
new PLL for 240MHz -> 50MHz. Used for calibration Clock on combiner board of CBM RICH (recovered 240MHz clock)
base/cores/ecp3/PLL/pll_in240_out50.ipx [new file with mode: 0644]
base/cores/ecp3/PLL/pll_in240_out50.lpc [new file with mode: 0644]
base/cores/ecp3/PLL/pll_in240_out50.vhd [new file with mode: 0644]