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(parent: ed1861e) | patch
small changes to fix data written to fifo in hub logic. Before, first word was writte...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 3 Mar 2021 10:13:30 +0000 (11:13 +0100)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 3 Mar 2021 10:13:30 +0000 (11:13 +0100)
commitf6b5ef0583f6bf8611622abddbbfa67c322c6edb
tree4d503afa4fdb3ec5af0735aecb6926304268d185tree | snapshot
parented1861e2cb7d7438f437ddf7bee2630ef0bb3a1ccommit | diff
small changes to fix data written to fifo in hub logic. Before, first word was written to rx fifo in hub logic twice.
src/cri_trbnet_dca_bridge.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware