]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/commit
jspc29 / dirich.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: a06894c) | patch
Pll and reset handler for 240MHz on ECP5
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 4 May 2022 14:32:20 +0000 (16:32 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 4 May 2022 14:32:20 +0000 (16:32 +0200)
commitf71c672ca848f0ebd8702a30c9da087cea7a4c85
tree5b1081ef97186b1dc6287d58ff28c310d7697f98tree | snapshot
parenta06894cb114169d612a5e8e03b7deca943fbf8b2commit | diff
Pll and reset handler for 240MHz on ECP5
code/clock_reset_handler_240.vhd [new file with mode: 0644] blob
cores/ecp5/pll_200_240.ipx [new file with mode: 0644] blob
cores/ecp5/pll_200_240.lpc [new file with mode: 0644] blob
cores/ecp5/pll_200_240.vhd [new file with mode: 0644] blob
DiRich front-end and related