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(parent: 66dc4e0) | patch
Changes in the code and constraint to meet the timing
authorCahit <c.ugur@gsi.de>
Fri, 28 Feb 2014 19:29:26 +0000 (20:29 +0100)
committerCahit <c.ugur@gsi.de>
Fri, 28 Feb 2014 19:29:26 +0000 (20:29 +0100)
commitf9b3dd18d99e06f68d36d927cb2056bfad4666ae
tree5a28319eb0f8847480d5ed0bc30cce8d2fa3083etree | snapshot
parent66dc4e0b548b9fcb1ab545e6f2e4e83ec792cbbccommit | diff
Changes in the code and constraint to meet the timing
32PinAddOn/compile_periph_gsi.pl diff | blob | history
32PinAddOn/nodes_lxhadeb07.txt diff | blob | history
32PinAddOn/trb3_periph_32PinAddOn.vhd diff | blob | history
tdc_releases/tdc_v1.6/Readout.vhd diff | blob | history
tdc_releases/tdc_v1.6/TDC.vhd diff | blob | history
tdc_releases/tdc_v1.6/tdc_constraints.lpf diff | blob | history
tdc_releases/tdc_v1.6/tdc_constraints_2.lpf [new file with mode: 0644] blob
tdc_releases/tdc_v1.6/trbnet_constraints.lpf diff | blob | history
TRB3 VHDL