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(parent: c0a08b0) | patch
added clock and trigger input selection to GbE design
authorJan Michel <j.michel@gsi.de>
Tue, 11 Feb 2014 17:48:30 +0000 (18:48 +0100)
committerJan Michel <j.michel@gsi.de>
Tue, 11 Feb 2014 17:50:24 +0000 (18:50 +0100)
commitfb114fc141f743b9706fe9234ac2cd4262e2edd0
treeb9f7ad8d01db19f11a65a1b55824046bf788e591tree | snapshot
parentc0a08b027b6334b806509d2b30517975dd0e010ecommit | diff
added clock and trigger input selection to GbE design
trb3_gbe/trb3_central.vhd diff | blob | history
TRB3 VHDL