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(parent: 6271736) | patch
dirich5s1 new reset routine and more stable CDR settings, mt dirich5s1_new_reset_cdr_fix
authorHADES DAQ <M.Traxler@gsi.de>
Tue, 4 Apr 2023 17:29:19 +0000 (19:29 +0200)
committerHADES DAQ <M.Traxler@gsi.de>
Tue, 4 Apr 2023 17:29:19 +0000 (19:29 +0200)
commit332a0d96bbce0deb241dfcaf5a305d55ccda9ff9
tree89016fe762f020ba993f5255c1c88df712afbab8tree | snapshot
parent6271736cb401f87139736060800fb6510cb5bd65commit | diff
dirich5s1 new reset routine and more stable CDR settings, mt
media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx [deleted file] blob | history
media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc diff | blob | history
media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd diff | blob | history
media_interfaces/med_ecp5_sfp_sync.vhd diff | blob | history
media_interfaces/sync/med_sync_control.vhd diff | blob | history
media_interfaces/sync/med_sync_define.vhd diff | blob | history
TrbNet VHDL code