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Changes the pinout (and some of the code) of the dirich5d_piggy to make it compatible... master
authorManuel Reyes <m.reyes@gsi.de>
Tue, 25 Jun 2024 11:41:09 +0000 (13:41 +0200)
committerManuel Reyes <m.reyes@gsi.de>
Tue, 25 Jun 2024 11:41:09 +0000 (13:41 +0200)
commitb37d783389ccc72e0f1b983be9424d9f5a033fea
treeef75a136fc9d32ee913ce77afb7842ebc9dd9c21tree | snapshot
parent8401f2dc280525834e5d42677717325b90596be1commit | diff
Changes the pinout (and some of the code) of the dirich5d_piggy to make it compatible with the DIRICH5D1_PIGGY2 layout. MReyes

The LVDS output pin-pair of channel 5 was changed to a true-LVDS pair, and one more pin was declared. An input signal was declared in the VHDL code.
dirich5d_piggy1_trigger/dirich5d_piggy1_trigger.lpf diff | blob | history
dirich5d_piggy1_trigger/dirich5d_piggy1_trigger1.vhd diff | blob | history
DiRich front-end and related