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(parent: 1b630db) | patch
RSL for SerDes, some ECP5 cores
authorMichael Boehmer <mboehmer@ph.tum.de>
Wed, 29 Jun 2022 15:51:27 +0000 (17:51 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Wed, 29 Jun 2022 15:51:27 +0000 (17:51 +0200)
commit0bbe1a10588fcf3c1090101e692de6c6133521d6
tree2baa3a7e9cbd166b43ea2784d4f7f475ad2c85eetree | snapshot
parent1b630db6cf75c693d98d72eebddd1b2064c4e29acommit | diff
RSL for SerDes, some ECP5 cores
gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.lpc [new file with mode: 0644] blob
gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd [new file with mode: 0644] blob
gbe_trb/ipcores/ecp5/fifo_64kx9.lpc [new file with mode: 0644] blob
gbe_trb/ipcores/ecp5/fifo_64kx9.vhd [new file with mode: 0644] blob
media_interfaces/sync/main_rx_reset_RS.vhd [new file with mode: 0644] blob
media_interfaces/sync/main_tx_reset_RS.vhd [new file with mode: 0644] blob
TrbNet VHDL code