-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
-add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
-
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire2.vhd"
-
-add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
-add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-add_file -vhdl -lib work "tdc_release/Channel.vhd"
-add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
-add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
-add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
-add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
-add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
-add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"