-print $handle_lastprog $initmem_folder;
-# #print "data registers for FPGA $fpga_addr:", map { "$_ => $drs_binary{$_}\n" } keys %drs_binary;
-# $drs_offset{$irs[0]} = 4+(scalar @irs)*2;
-# for (my $i=1;$i<@irs;$i++) {
-# my $dr_length = $drs_length{$irs[$i-1]};
-# $drs_offset{$irs[$i]} = $drs_offset{$irs[$i-1]} + floor(($dr_length*(scalar @sensors)+31)/32) + 2; # add one x 32 bit for CRC, one x 32 bit for IR, integer division rounds down, right?
-# }
-# #open RAMTEXT, ">$memfiles_prefix{$chain}";
-# $num_words = 0;
-# my $ram_fh;
-# my @mem_filenames;
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc (reverse(join('',unpack("h8", pack("L", scalar(@sensors)))))) . "\t# numchips \n"); # numchips; the reverse is done here because apparently internally the unsigned long is stored LSByte first (little endian)
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", 0))))) . "\t# reserved\n"); # reserved
-# for (my $i=0;$i<@irs;$i++) {
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_offset{$irs[$i]}))))) . "\t# pointer\n"); # pointer
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(join('',unpack("h8", pack("L", $drs_length{$irs[$i]}))))) . "\t# length \n"); # length
-# }
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# pointer (end of list)\n");
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x00000000\t# length (end of list)\n");
-# for (my $i=0;$i<@irs;$i++) {
-# my $ir=$irs[$i];
-# #print "ir: $ir\n";
-# my $ir_packed = pack("h*", (scalar reverse($ir)).("0"x (7-(length($ir)-1)%8)));
-# my $ir_packed_r = pack("B*", scalar reverse substr(unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))),0, 32));
-# #print "debug ir_packed (h*): ". (scalar reverse($ir)).("0"x (8-length($ir)%32))."\n";
-# #print "debug ir_packed_r (B*): ". scalar reverse unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
-# #print "debug2: " . (7-(length($ir)-1)%8) . "\n";
-# #print "debug3: " . $ir . "\n";
-# #print "debug4: " . $ir.("0"x (7-(length($ir)-1)%8)) . "\n";
-# #print "debug5 (B*): ". unpack("B*", pack("H*", $ir.("0"x (7-(length($ir)-1)%8)))) ."\n";
-#
-# my $initial = 0x00000000;
-# my $crc0 = crc32($ir_packed_r, $initial);
-# #printf "CRC0: %X. ~reversed: %X\n", $crc0, $crc0_rn;
-#
-# for(my $i=0; $i<floor((length($drs_binary{$ir})-1)/32)+1;$i++){
-# my $dr_word_packed_r = pack("b*", scalar reverse substr($drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)),($i)*32, 32));
-# $crc0 = crc32($dr_word_packed_r, $crc0);
-# my $crc0_rn = ~reverse32bit($crc0);
-# printf "CRC: 0x%0.8X.\n", $crc0_rn;
-# }
-# my $crc0_rn = ~reverse32bit($crc0);
-# #printf "CRC: %0.8X.\n", $crc0_rn, 1;
-# my $line_crc = sprintf "0x%0.8X\t# CRC-32\n", $crc0_rn;
-# print "debug dr_binary: " . $drs_binary{$ir} . "\n";
-# my $dr_packed = pack("b*", $drs_binary{$ir}.("0"x (31-(length($drs_binary{$ir})-1)%32)));
-# $drs{$ir} = unpack('h*', $dr_packed);
-# print "debug drs: " . $drs{$ir} . "\n";
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(8-length($ir))).uc($ir) . "\n");
-# for(my $i=0; $i<floor((length( $drs{$ir}) -1)/8)+1; $i++){
-# #print "dbg: i=$i, len=".length( $drs{$ir})."\n";
-# if(length($drs{$ir}) >= ($i+1)*8) {
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".uc(reverse(substr($drs{$ir}, ($i)*8, 8))) . "\n");
-# }
-# else {
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, "0x".("0"x(($i+1)*8-length($drs{$ir}))).uc(reverse(substr($drs{$ir}, ($i)*8, length($drs{$ir})%8))) . "\n");
-# }
-# }
-# memfile_writeline( $ram_fh, \@mem_filenames, $memfiles_prefix, $line_crc);
-#
-# #print "IR $ir, DR ". $drs{$ir} . "\n";
-# }
-# #close RAMTEXT;
-# $ram_fh->close();
-# #my $result = `cat $memfile{$fpga_addr}`;
-# $ENV{'DAQOPSERVER'}="trb126";
-# for(my $i=0;$i<scalar @mem_filenames;$i++) {
-# # write RAM base pointer
-# my $ihex = int_to_32bit_hex($i);
-# print "trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n";
-# my $result = `trbcmd w $fpga_addr $ram_base_addr 0x$ihex\n`;
-# print "set RAM base pointer: " . $result;
-# # write to configuration RAM
-# print "trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]\n";
-# $result = `trbcmd wm $fpga_addr $ram_addr 0 $mem_filenames[$i]`;
-# print "write max. 256 32-bit-words: " . $result;
-# }
-#}
-
-
-# init_writemem:
-# - loop through chains
-# - loop through sensors
-# - test if IR length is the same as for other sensors
-# - loop through DRs
-# - test if DR length is the same as for other sensors
-# - add DR content to chain data register (hexadecimal string)
-# - write contents for JTAG chain controller RAM to text file(s)
-# - execute trbcmd to transfer file(s) to RAM of FPGA configured in chains.ini
-#
-# get_status:
-# get_error_counts:
-# reactivate_sensor:
-# deactivate_sensor: