Add input counters to logicbox and new and/or output mode.

diff --git a/default/config_compile_frankfurt.pl b/default/config_compile_frankfurt.pl
index ec5cb2bd3204f2d976f16cdd32dcfb823c41591f..a9d1489b24f81435e4d547e1248de8e7b48eb2c6 100644 (file)
--- a/default/config_compile_frankfurt.pl
+++ b/default/config_compile_frankfurt.pl
@@ -6,8 +6,8 @@ Speedgrade  => '5',
 TOPNAME                      => "logicbox",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 TOPNAME                      => "logicbox",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",

-lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/N-2017.09-1',

 # synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
 # synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",

diff --git a/default/logicbox.prj b/default/logicbox.prj
index 2b1374f1cb146956479900a5787b7e306a842e46..ee99ae2518fc8ae4de066f03e237bb88b50caf67 100644 (file)
--- a/default/logicbox.prj
+++ b/default/logicbox.prj
@@ -16,7 +16,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"

-add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"

 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 
 add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 
 add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index 798d99d4072e0f47d16ed4d2cff5469e869b0119..69d1af4ce354aa764347c96e562e36a22dcdd096 100644 (file)
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -61,6 +61,7 @@ architecture arch of logicbox is
   signal input_selected  : std_logic_vector(3 downto 0); 
   signal input_stretched, input_hold : std_logic_vector(3 downto 0);
   signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);
   signal input_selected  : std_logic_vector(3 downto 0); 
   signal input_stretched, input_hold : std_logic_vector(3 downto 0);
   signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);

+  signal input_and, input_or : std_logic;

  
   signal edge_rising, edge_falling : std_logic_vector(3 downto 0);
   signal reg         : std_logic_vector(31 downto 0);
  
   signal edge_rising, edge_falling : std_logic_vector(3 downto 0);
   signal reg         : std_logic_vector(31 downto 0);


@@ -69,8 +70,12 @@ architecture arch of logicbox is
   signal sed_error : std_logic;
   signal sed_debug : std_logic_vector(31 downto 0);
   signal controlsed_i : std_logic_vector(3 downto 0);
   signal sed_error : std_logic;
   signal sed_debug : std_logic_vector(31 downto 0);
   signal controlsed_i : std_logic_vector(3 downto 0);

-  signal testreg1, testreg2 : std_logic_vector(31 downto 0);
+  signal reset_counters : std_logic;
+
+  signal disabled_inp : std_logic_vector(3 downto 0) := x"0";

   
   

+  type cnt_t is array(0 to 3) of unsigned(23 downto 0);
+  signal input_counters : cnt_t;

   
   --PULSER
   -------------------------------------  
   
   --PULSER
   -------------------------------------  


@@ -81,17 +86,6 @@ architecture arch of logicbox is
   signal pulser_periodlength_buffer : unsigned(27 downto 0);
   signal pulser_pulslength_buffer : unsigned(27 downto 0);
 
   signal pulser_periodlength_buffer : unsigned(27 downto 0);
   signal pulser_pulslength_buffer : unsigned(27 downto 0);
 

-  --UFM
-  -------------------------------------
-  --signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write
-  --signal ufm_go : std_logic := '1'; --load default values to registers from UFM at startup 
-  --signal ufm_data_in : std_logic_vector(7 downto 0); --directly connected to flashram DataInA
-  --signal ufm_data_out : std_logic_vector(7 downto 0); --directly connected to flashram QB
-  --signal ufm_databyte_counter : unsigned(14 downto 0);
-  --signal ufm_bus_ready_out : std_logic;
-  --signal ufm_bus_ready_in : std_logic;
-  --signal ufm_busy : std_logic;
-

   
   component OSCH
     generic (NOM_FREQ: string := "133.00");
   
   component OSCH
     generic (NOM_FREQ: string := "133.00");


@@ -123,11 +117,14 @@ begin
 -- 9    1:4 fan-out, stretching
 -- a    1:1, O1 is or of inputs, stretching
 
 -- 9    1:4 fan-out, stretching
 -- a    1:1, O1 is or of inputs, stretching
 

+-- b    O0 is and, O2 is or of all enabled outputs
+-- c    like b, but inverted inputs
+

 -- e    pulser, default 8.1 kHz, 60ns 
 -- f    pulser, default 8.1 kHz, 60ns, negative
 
 input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1);
 -- e    pulser, default 8.1 kHz, 60ns 
 -- f    pulser, default 8.1 kHz, 60ns, negative
 
 input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1);

-input_selected <= not input_i when config = x"3" or config = x"4" or config = x"5" else input_i;
+input_selected <= not input_i when config = x"3" or config = x"4" or config = x"5" or config = x"c" else input_i;

 
 input_stretched <= input_hold or input_reg_0 or input_reg_1;
 
 
 input_stretched <= input_hold or input_reg_0 or input_reg_1;
 


@@ -141,6 +138,17 @@ input_reg_2 <= input_reg_1 when rising_edge(clk_i);
 edge_rising  <= input_stretched and not input_reg_2;
 edge_falling <= not input_stretched and input_reg_2;
 
 edge_rising  <= input_stretched and not input_reg_2;
 edge_falling <= not input_stretched and input_reg_2;
 

+input_and <=    (input_selected(0) or disabled_inp(0)) 
+            and (input_selected(1) or disabled_inp(1))
+            and (input_selected(2) or disabled_inp(2))
+            and (input_selected(3) or disabled_inp(3));
+
+input_or  <=   (input_selected(0) and not disabled_inp(0)) 
+            or (input_selected(1) and not disabled_inp(1))
+            or (input_selected(2) and not disabled_inp(2))
+            or (input_selected(3) and not disabled_inp(3));
+            
+            

 process(INPUT,config, STATUSI)
   begin
     case config is 
 process(INPUT,config, STATUSI)
   begin
     case config is 


@@ -167,6 +175,10 @@ process(INPUT,config, STATUSI)
         OUTPUT <= (others => input_stretched(0));
       when x"a" =>
         OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0);
         OUTPUT <= (others => input_stretched(0));
       when x"a" =>
         OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0);

+      when x"b" =>
+        OUTPUT <= '0' & input_or & '0' & input_and;
+      when x"c" =>
+        OUTPUT <= '0' & input_or & '0' & input_and;

       when x"e" =>
         OUTPUT <= (others => pulser);
       when x"f" =>
       when x"e" =>
         OUTPUT <= (others => pulser);
       when x"f" =>


@@ -225,6 +237,22 @@ process(INPUT,config, STATUSI)
       end if;
     end loop;
   end process;  
       end if;
     end loop;
   end process;  

+
+---------------------------------------------------------------------------
+-- Counter
+---------------------------------------------------------------------------  
+  PROC_CNT : process begin
+    wait until rising_edge(clk_i);
+    for i in 0 to 3 loop
+      if input_reg_1(i) = '1' and input_reg_2(i) = '0' then
+        input_counters(i) <= input_counters(i) + 1;
+      end if;  
+      if reset_counters = '1' then
+        input_counters(i) <= (others => '0');
+      end if;  
+    end loop;
+  end process;
+  

   
 ---------------------------------------------------------------------------
 -- Clock
   
 ---------------------------------------------------------------------------
 -- Clock


@@ -264,7 +292,6 @@ process begin
 end process;  
 
 LED <= led_i when led_highz = '0' else "ZZZZ";
 end process;  
 
 LED <= led_i when led_highz = '0' else "ZZZZ";

--- LED <= sed_debug(3 downto 0);

 
 ---------------------------------------------------------------------------
 -- UART
 
 ---------------------------------------------------------------------------
 -- UART


@@ -290,13 +317,6 @@ THE_UART : entity work.uart_sctrl
     DEBUG     => open
     );
 
     DEBUG     => open
     );
 

---uart_rx_data <= uart_data_out;
---uart_data_in <= uart_tx_data;
---uart_addr    <= uart_addr_out;
---bus_write    <= uart_write_out;
---bus_read     <= uart_read_out;
---uart_ready_in <= bus_ready;
---bus_busy     <= uart_busy_out;

 
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   generic map(
 
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   generic map(


@@ -336,6 +356,7 @@ PROC_REGS : process begin
   --register <=> UART datatransfer
   -------------------------------------------------------------------
   bus_ready <= '0';
   --register <=> UART datatransfer
   -------------------------------------------------------------------
   bus_ready <= '0';

+  reset_counters <= '0';

 --  ufm_go <= '0'; --for operating UFM_control
     
   if bus_read = '1' then
 --  ufm_go <= '0'; --for operating UFM_control
     
   if bus_read = '1' then


@@ -343,14 +364,16 @@ PROC_REGS : process begin
     bus_ready <= '1';
     case uart_addr is
       when x"00" => uart_tx_data <= x"0000000" & config;
     bus_ready <= '1';
     case uart_addr is
       when x"00" => uart_tx_data <= x"0000000" & config;

-      when x"10" => uart_tx_data <= reg;
+      when x"10" => uart_tx_data <= x"0000000" & disabled_inp;

       when x"ee" => uart_tx_data <= sed_debug;
       
       when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);
       when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);
 
       when x"ee" => uart_tx_data <= sed_debug;
       
       when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);
       when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);
 

-      when x"ff" => uart_tx_data <= testreg1;              
-      when x"fe" => uart_tx_data <= testreg2;                    
+      when x"30" => uart_tx_data <= x"00" & std_logic_vector(input_counters(0));
+      when x"31" => uart_tx_data <= x"00" & std_logic_vector(input_counters(1));
+      when x"32" => uart_tx_data <= x"00" & std_logic_vector(input_counters(2));
+      when x"33" => uart_tx_data <= x"00" & std_logic_vector(input_counters(3));

                     
       when others => uart_tx_data <= x"00000000";
     end case;
                     
       when others => uart_tx_data <= x"00000000";
     end case;


@@ -358,112 +381,34 @@ PROC_REGS : process begin
   elsif bus_write = '1' then
   --write registers with data from received from RS232
     case uart_addr is
   elsif bus_write = '1' then
   --write registers with data from received from RS232
     case uart_addr is

---      when x"02" => if uart_rx_data = x"00000000" and ufm_busy = '0' then 
-                    --initiate load from UFM
---                      ufm_cmd <= '0';
---                      ufm_go <= '1';-
---                    elsif uart_rx_data  = x"FFFFFFFF" and ufm_busy = '0' then
---                    --initiate write to UFM
---                      ufm_cmd <= '1';
---                      ufm_go <= '1';
---                    end if; 

     
     

-      when x"10" => reg <= uart_rx_data;
+      when x"10" => disabled_inp <= uart_rx_data(3 downto 0);

 
       when x"20" => if uart_rx_data = x"00000000" or  uart_rx_data = x"00000001" then
                       pulser_periodlength <= x"0000001";
                     else
                       pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1;
                     end if;
 
       when x"20" => if uart_rx_data = x"00000000" or  uart_rx_data = x"00000001" then
                       pulser_periodlength <= x"0000001";
                     else
                       pulser_periodlength <= unsigned(uart_rx_data(27 downto 0)) - 1;
                     end if;

-      

       when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);
       when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);

+
+      when x"30" => reset_counters <= '1';

       
       when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);
 
       
       when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);
 

-      when x"ff" => testreg1 <= uart_rx_data(31 downto 0);
-      when x"fe" => testreg2 <= uart_rx_data(31 downto 0);
-                    

       when others => null;
     end case;
   end if;
   
       when others => null;
     end case;
   end if;
   

-  --register <=> UFM datatransfer
-  -------------------------------------------------------------------
---  ufm_bus_ready_in <= '0'; 
-
---  if ufm_cmd = '0' and ufm_bus_ready_out = '1' then
-  --copy data from UFM to registers
---    ufm_bus_ready_in <= '1';
---    case to_integer(ufm_databyte_counter) is
---      when 0 =>   reg(7 downto 0) <= ufm_data_out;
---      when 1 =>   reg(15 downto 8) <= ufm_data_out;
---      when 2 =>   reg(23 downto 16) <= ufm_data_out;
---      when 3 =>   reg(31 downto 24) <= ufm_data_out;
-      
---      when 4 =>   pulser_periodlength(7 downto 0) <= ufm_data_out;
---      when 5 =>   pulser_periodlength(15 downto 8) <= ufm_data_out;
---      when 6 =>   pulser_periodlength(23 downto 16) <= ufm_data_out;
---      when 7 =>   pulser_periodlength(27 downto 24) <= ufm_data_out(3 downto 0);
-      
---      when 8 =>   pulser_pulslength(7 downto 0) <= ufm_data_out;
---      when 9 =>   pulser_pulslength(15 downto 8) <= ufm_data_out;
---      when 10 =>  pulser_pulslength(23 downto 16) <= ufm_data_out;
---      when 11 =>  pulser_pulslength(27 downto 24) <= ufm_data_out(3 downto 0);
-      
---      when others =>null;
---    end case;
-      
---  elsif ufm_cmd = '1' and ufm_bus_ready_out = '1' then
-  --save data from registers to UFM
---    ufm_bus_ready_in <= '1';
---    case to_integer(ufm_databyte_counter) is
---      when 0 =>   ufm_data_in <= reg(7 downto 0);
---      when 1 =>   ufm_data_in <= reg(15 downto 8);
---      when 2 =>   ufm_data_in <= reg(23 downto 16);
---      when 3 =>   ufm_data_in <= reg(31 downto 24);
-
---      when 4 =>   ufm_data_in <= pulser_periodlength(7 downto 0);
---      when 5 =>   ufm_data_in <= pulser_periodlength(15 downto 8);
---      when 6 =>   ufm_data_in <= pulser_periodlength(23 downto 16);
---      when 7 =>   ufm_data_in <= x"0" & std_logic_vector(pulser_periodlength(27 downto 24));
-      
---      when 8 =>   ufm_data_in <= pulser_pulslength(7 downto 0);
---      when 9 =>   ufm_data_in <= pulser_pulslength(15 downto 8);
---      when 10 =>  ufm_data_in <= pulser_pulslength(23 downto 16);
---      when 11 =>  ufm_data_in <= x"0" & std_logic_vector(pulser_pulslength(27 downto 24));
-      
---      when others =>null;
---    end case;
-      
---  end if;

 end process;
 
 
 end process;
 
 

- THE_SED : entity work.sedcheck
-   port map(
-     CLK        => clk_i,
-     ERROR_OUT  => sed_error,
-     
-     CONTROL_IN => controlsed_i,
-     DEBUG      => sed_debug
-     );
-
---   process begin
---     wait until rising_edge(clk_i);
---     if counter = x"40" then
---       counter <= 0;
---       pwm <= '1';
---     else  
---       counter <= counter + 1;
---       pwm <= '0';
---     end if; 
---   end process;
---     
---     
---     OUTPUT <= '0' & pwm & '0' & pwm;
---     CONTROLO <= pwm;
-    
-end architecture;
+--  THE_SED : entity work.sedcheck
+--    port map(
+--      CLK        => clk_i,
+--      ERROR_OUT  => sed_error,
+--      
+--      CONTROL_IN => controlsed_i,
+--      DEBUG      => sed_debug
+--      );

 
 

-       
-       
+end architecture;