+<<<<<<< hub2_fpga2.vhd
+--Port 19&20 is uplink, Port 18 is downlinks, 17 is reserved for Ethernet
+
+--the hub logic reports
+--sfp 18 = port 0
+--sfp 19 = port 1 Slowcontrol
+--lvds = port 2 to FPGA1
+--sfp 20 = port 3 CTS
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+
+
+entity hub2_fpga2 is
+generic( USE_ETHERNET : integer range c_NO to c_YES := c_YES;
+ USE_200_MHZ : integer range c_NO to c_YES := c_YES
+ );
+port(
+-- CLK_F2_TO_F1 : out std_logic; -- unused
+ CLK_F1_TO_F2 : in std_logic;
+-- ADDON_RESET : in std_logic; -- unused
+-- RESET_N : in std_logic; -- unused
+-- SUPPL_RESET_N : in std_logic; -- unused
+ --Connection to TRB
+-- ADO_LV : inout std_logic_vector(61 downto 0);
+-- ADO_TTL : inout std_logic_vector(45 downto 0);
+ --Connection to FPGA1
+ F1_TO_F2 : in std_logic_vector(31 downto 0);
+ F2_TO_F1 : out std_logic_vector(31 downto 0);
+ --Optical Links
+ SFP_TXP : out std_logic_vector(20 downto 17);
+ SFP_TXN : out std_logic_vector(20 downto 17);
+ SFP_RXP : in std_logic_vector(20 downto 17);
+ SFP_RXN : in std_logic_vector(20 downto 17);
+ SFP_REFCLKP : in std_logic_vector(20 downto 17);
+ SFP_REFCLKN : in std_logic_vector(20 downto 17);
+ SFP_LED_GREEN : out std_logic_vector(20 downto 17);
+ SFP_LED_ORANGE : out std_logic_vector(20 downto 17);
+ SFP_MOD0 : in std_logic_vector(20 downto 17);
+ SFP_LOS : in std_logic_vector(20 downto 17);
+ SFP_DIS : out std_logic_vector(20 downto 17);
+ --Other
+ ONEWIRE_MONITOR_IN : in std_logic;
+ --Debugging
+ TEST_2 : out std_logic_vector(31 downto 0)
+);
+
+attribute syn_useioff : boolean;
+attribute syn_useioff of F1_TO_F2 : signal is true;
+attribute syn_useioff of F2_TO_F1 : signal is true;
+
+attribute syn_useioff of SFP_LED_GREEN : signal is false;
+attribute syn_useioff of SFP_LED_ORANGE : signal is false;
+
+end entity;
+
+architecture hub2_fpga2_arch of hub2_fpga2 is
+
+component trb_net16_gbe_buf is
+generic(
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
+);
+port(
+ CLK : in std_logic;
+ TEST_CLK : in std_logic; -- only for simulation!
+ CLK_125_TX_IN : in std_logic; -- gk 28.04.01
+ CLK_125_RX_IN : in std_logic; -- gk 28.04.01
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ -- Debug
+ STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);
+ STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);
+ -- configuration interface
+ IP_CFG_START_IN : in std_logic;
+ IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);
+ IP_CFG_DONE_OUT : out std_logic;
+ IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);
+ IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);
+ IP_CFG_MEM_CLK_OUT : out std_logic;
+ MR_RESET_IN : in std_logic;
+ MR_MODE_IN : in std_logic;
+ MR_RESTART_IN : in std_logic;
+ -- gk 29.03.10
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- gk 26.04.10
+ -- registers setup interface
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ BUS_WRITE_EN_IN : in std_logic;
+ BUS_READ_EN_IN : in std_logic;
+ BUS_ACK_OUT : out std_logic;
+ -- gk 23.04.10
+ LED_PACKET_SENT_OUT : out std_logic;
+ LED_AN_DONE_N_OUT : out std_logic;
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
+ CTS_CODE_IN : in std_logic_vector(7 downto 0);
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);
+ CTS_START_READOUT_IN : in std_logic;
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic;
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0);
+ FEE_DATAREADY_IN : in std_logic;
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ FEE_BUSY_IN : in std_logic;
+ --SFP Connection
+ SFP_RXD_P_IN : in std_logic;
+ SFP_RXD_N_IN : in std_logic;
+ SFP_TXD_P_OUT : out std_logic;
+ SFP_TXD_N_OUT : out std_logic;
+ SFP_REFCLK_P_IN : in std_logic;
+ SFP_REFCLK_N_IN : in std_logic;
+ SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SFP_TXDIS_OUT : out std_logic; -- SFP disable
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- PacketConstructor interface
+ IG_CTS_CTR_TST : out std_logic_vector(2 downto 0);
+ IG_REM_CTR_TST : out std_logic_vector(3 downto 0);
+ IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0);
+ IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0);
+ IG_DATA_TST : out std_logic_vector(15 downto 0);
+ IG_WCNT_TST : out std_logic_vector(15 downto 0);
+ IG_RCNT_TST : out std_logic_vector(16 downto 0);
+ IG_RD_EN_TST : out std_logic;
+ IG_WR_EN_TST : out std_logic;
+ IG_EMPTY_TST : out std_logic;
+ IG_AEMPTY_TST : out std_logic;
+ IG_FULL_TST : out std_logic;
+ IG_AFULL_TST : out std_logic;
+ PC_WR_EN_TST : out std_logic;
+ PC_DATA_TST : out std_logic_vector (7 downto 0);
+ PC_READY_TST : out std_logic;
+ PC_START_OF_SUB_TST : out std_logic;
+ PC_END_OF_DATA_TST : out std_logic;
+ PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0);
+ PC_TRIG_NR_TST : out std_logic_vector(31 downto 0);
+ PC_PADDING_TST : out std_logic;
+ PC_DECODING_TST : out std_logic_vector(31 downto 0);
+ PC_EVENT_ID_TST : out std_logic_vector(31 downto 0);
+ PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0);
+ PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0);
+ PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0);
+ PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0);
+ PC_SHF_EMPTY_TST : out std_logic;
+ PC_SHF_FULL_TST : out std_logic;
+ PC_DF_EMPTY_TST : out std_logic;
+ PC_DF_FULL_TST : out std_logic;
+ PC_ALL_CTR_TST : out std_logic_vector(4 downto 0);
+ PC_SUB_CTR_TST : out std_logic_vector(4 downto 0);
+ PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0);
+ PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0);
+ PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0);
+ PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0);
+ PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameConstructor interface
+ FC_WR_EN_TST : out std_logic;
+ FC_DATA_TST : out std_logic_vector(7 downto 0);
+ FC_H_READY_TST : out std_logic;
+ FC_READY_TST : out std_logic;
+ FC_IP_SIZE_TST : out std_logic_vector(15 downto 0);
+ FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0);
+ FC_IDENT_TST : out std_logic_vector(15 downto 0);
+ FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0);
+ FC_SOD_TST : out std_logic;
+ FC_EOD_TST : out std_logic;
+ FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0);
+ FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameTransmitter interface
+ FT_DATA_TST : out std_logic_vector(8 downto 0);
+ FT_TX_EMPTY_TST : out std_logic;
+ FT_START_OF_PACKET_TST : out std_logic;
+ FT_BSM_INIT_TST : out std_logic_vector(3 downto 0);
+ FT_BSM_MAC_TST : out std_logic_vector(3 downto 0);
+ FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0);
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- MAC interface
+ MAC_HADDR_TST : out std_logic_vector(7 downto 0);
+ MAC_HDATA_TST : out std_logic_vector(7 downto 0);
+ MAC_HCS_TST : out std_logic;
+ MAC_HWRITE_TST : out std_logic;
+ MAC_HREAD_TST : out std_logic;
+ MAC_HREADY_TST : out std_logic;
+ MAC_HDATA_EN_TST : out std_logic;
+ MAC_FIFOAVAIL_TST : out std_logic;
+ MAC_FIFOEOF_TST : out std_logic;
+ MAC_FIFOEMPTY_TST : out std_logic;
+ MAC_TX_READ_TST : out std_logic;
+ MAC_TX_DONE_TST : out std_logic;
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- pcs and serdes
+ PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0);
+ PCS_AN_COMPLETE_TST : out std_logic;
+ PCS_AN_PAGE_RX_TST : out std_logic;
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- debug ports
+ ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
+);
+end component;
+
+component slv_register is
+generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );
+port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ BUSY_IN : in std_logic;
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- I/O to the backend
+ REG_DATA_IN : in std_logic_vector(31 downto 0);
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- Status lines
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG
+);
+end component;
+
+component slv_mac_memory is
+port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ BUSY_IN : in std_logic;
+ -- Slave bus
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_BUSY_OUT : out std_logic;
+ SLV_ACK_OUT : out std_logic;
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- I/O to the backend
+ MEM_CLK_IN : in std_logic;
+ MEM_ADDR_IN : in std_logic_vector(7 downto 0);
+ MEM_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- Status lines
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG
+);
+end component;
+
+constant mii : integer := 4;
+
+-- Clocks and reset
+signal clk_in : std_logic; -- clock from SerDes reference output (100MHz or 200MHz)
+signal clk_100 : std_logic; -- 100MHz system clock
+signal clk_en : std_logic;
+signal reset_i_q : std_logic; -- fast async reset for SerDes
+signal pll_locked : std_logic;
+signal reset_counter : std_logic_vector(11 downto 0);
+signal next_reset : std_logic;
+signal reset_i : std_logic;
+signal make_reset_via_network_q : std_logic;
+signal make_reset_via_network : std_logic;
+signal gsr_n : std_logic;
+
+signal test_clk : std_logic; -- MUST BE ZERO!!!
+
+signal buf_SFP_LOS : std_logic_vector(20 downto 17);
+signal buf_SFP_MOD0 : std_logic_vector(20 downto 17);
+
+signal med_data_in : std_logic_vector(4*16-1 downto 0);
+signal med_data_out : std_logic_vector(4*16-1 downto 0);
+signal med_packet_num_in : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+signal med_packet_num_out : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+signal med_dataready_in : std_logic_vector(3 downto 0);
+signal med_dataready_out : std_logic_vector(3 downto 0);
+signal med_read_in : std_logic_vector(3 downto 0);
+signal med_read_out : std_logic_vector(3 downto 0);
+
+signal med_stat_op : std_logic_vector(4*16-1 downto 0);
+signal med_ctrl_op : std_logic_vector(4*16-1 downto 0);
+signal med_stat_debug : std_logic_vector(4*64-1 downto 0);
+signal med_ctrl_debug : std_logic_vector(4*64-1 downto 0);
+
+signal buf_SFP_LED_ORANGE : std_logic_vector(20 downto 17);
+signal buf_SFP_LED_GREEN : std_logic_vector(20 downto 17);
+
+signal cts_number : std_logic_vector(15 downto 0);
+signal cts_code : std_logic_vector(7 downto 0);
+signal cts_information : std_logic_vector(7 downto 0);
+signal cts_start_readout : std_logic;
+signal cts_readout_type : std_logic_vector(3 downto 0);
+signal cts_data : std_logic_vector(31 downto 0);
+signal cts_dataready : std_logic;
+signal cts_readout_finished : std_logic;
+signal cts_read : std_logic;
+signal cts_length : std_logic_vector(15 downto 0);
+signal cts_status_bits : std_logic_vector(31 downto 0);
+signal fee_data : std_logic_vector(15 downto 0);
+signal fee_dataready : std_logic;
+signal fee_read : std_logic;
+signal fee_status_bits : std_logic_vector(31 downto 0);
+signal fee_busy : std_logic;
+signal my_address : std_logic_vector(15 downto 0);
+
+signal stage_stat_regs : std_logic_vector (31 downto 0);
+signal stage_ctrl_regs : std_logic_vector (31 downto 0);
+
+--REGIO INTERFACE
+signal regio_addr_out : std_logic_vector(16-1 downto 0);
+signal regio_read_enable_out : std_logic;
+signal regio_write_enable_out : std_logic;
+signal regio_data_out : std_logic_vector(32-1 downto 0);
+signal regio_data_in : std_logic_vector(32-1 downto 0) := (others => '0');
+signal regio_dataready_in : std_logic := '0';
+signal regio_no_more_data_in : std_logic := '0';
+signal regio_write_ack_in : std_logic := '0';
+signal regio_unknown_addr_in : std_logic := '0';
+signal regio_timeout_out : std_logic;
+
+signal mb_ctrl_reg_data_wr : std_logic_vector(31 downto 0);
+signal mb_ctrl_reg_data_rd : std_logic_vector(31 downto 0);
+signal mb_ctrl_reg_read : std_logic;
+signal mb_ctrl_reg_write : std_logic;
+signal mb_ctrl_reg_ack : std_logic;
+
+signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0);
+signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0);
+signal mb_stat_reg_read : std_logic;
+signal mb_stat_reg_write : std_logic;
+signal mb_stat_reg_ack : std_logic;
+
+signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used
+signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0);
+signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0);
+signal mb_ip_mem_read : std_logic;
+signal mb_ip_mem_write : std_logic;
+signal mb_ip_mem_ack : std_logic;
+
+signal ip_cfg_mem_clk : std_logic;
+signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
+signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
+
+signal buf_test : std_logic_vector(31 downto 0);
+
+signal analyzer_debug : std_logic_vector(63 downto 0);
+
+-- gk 22.04.10
+signal ctrl_reg_addr : std_logic_vector(15 downto 0);
+signal gbe_stp_reg_addr : std_logic_vector(15 downto 0);
+signal gbe_stp_data : std_logic_vector(31 downto 0);
+signal gbe_stp_reg_ack : std_logic;
+signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0);
+signal gbe_stp_reg_read : std_logic;
+signal gbe_stp_reg_write : std_logic;
+signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0);
+
+begin
+
+---------------------------------------------------------------------
+-- Clock
+---------------------------------------------------------------------
+gen_no_pll : if USE_200_MHZ = c_NO generate
+THE_PLL : pll_in100_out100
+port map( CLK => clk_in,
+ CLKOP => clk_100,
+ LOCK => pll_locked
+ );
+end generate;
+
+gen_pll : if USE_200_MHZ = c_YES generate
+THE_PLL : pll_in200_out100
+port map( CLK => clk_in,
+ CLKOP => clk_100,
+ LOCK => pll_locked
+ );
+end generate;
+
+clk_en <= '1';
+test_clk <= '0';
+
+---------------------------------------------------------------------
+-- Reset process
+---------------------------------------------------------------------
+THE_RESET_COUNTER_PROC: process( pll_locked, clk_100 )
+begin
+ if( pll_locked = '0' ) then
+ -- asynchronous reset by PLL lock signal only
+ reset_counter <= (others => '0');
+ next_reset <= '1';
+ elsif( rising_edge(clk_100) ) then
+ if ( make_reset_via_network_q = '1' ) then
+ -- synchronous reset by network
+ reset_counter <= (others => '0');
+ next_reset <= '1';
+ elsif( reset_counter = x"EEE" ) then
+ reset_counter <= x"EEE";
+ next_reset <= '0';
+ else
+ reset_counter <= reset_counter + 1;
+ next_reset <= '1';
+ end if;
+ end if;
+end process THE_RESET_COUNTER_PROC;
+
+-- Fast aysnchronous reset for SerDes
+reset_i_q <= not pll_locked;
+
+gsr_n <= pll_locked;
+
+-- "normal" synchronous reset signal
+reset_i <= next_reset;
+
+-- reset by TRBnet (port 0 and 3 are uplinks)
+make_reset_via_network <= MED_STAT_OP(3*16+13) or MED_STAT_OP(0*16+13);
+
+THE_RESET_TRG_SYNC: signal_sync
+generic map(
+ DEPTH => 2,
+ WIDTH => 1 )
+port map(
+ RESET => '0',
+ D_IN(0) => make_reset_via_network,
+ CLK0 => clk_100,
+ CLK1 => clk_100,
+ D_OUT(0) => make_reset_via_network_q
+);
+
+---------------------------------------------------------------------
+-- Serdes
+---------------------------------------------------------------------
+
+-- Input synchronization
+THE_SFP_LOS_PROC: process( clk_100 )
+begin
+ if( rising_edge(clk_100) ) then
+ buf_SFP_LOS <= SFP_LOS;
+ buf_SFP_MOD0 <= SFP_MOD0;
+ end if;
+end process THE_SFP_LOS_PROC;
+
+---------------------------------------------------------------------
+-- one normal port (SFP18)
+---------------------------------------------------------------------
+THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe
+generic map(
+ SERDES_NUM => 0,
+ USE_200_MHZ => USE_200_MHZ
+)
+port map(
+ CLK => clk_in,
+ SYSCLK => clk_100,
+ RESET => reset_i,
+ CLEAR => reset_i_q,
+ CLK_EN => clk_en,
+ MED_DATA_IN => med_data_out(1*16-1 downto 0*16),
+ MED_PACKET_NUM_IN => med_packet_num_out(1*3-1 downto 0*3),
+ MED_DATAREADY_IN => med_dataready_out(0),
+ MED_READ_OUT => med_read_in(0),
+ MED_DATA_OUT => med_data_in(1*16-1 downto 0*16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(1*3-1 downto 0*3),
+ MED_DATAREADY_OUT => med_dataready_in(0),
+ MED_READ_IN => med_read_out(0),
+ REFCLK2CORE_OUT => open,
+ SD_RXD_P_IN => SFP_RXP(18),
+ SD_RXD_N_IN => SFP_RXN(18),
+ SD_TXD_P_OUT => SFP_TXP(18),
+ SD_TXD_N_OUT => SFP_TXN(18),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => buf_SFP_MOD0(18),
+ SD_LOS_IN => buf_SFP_LOS(18),
+ SD_TXDIS_OUT => SFP_DIS(18),
+ STAT_OP => med_stat_op(1*16-1 downto 0*16),
+ CTRL_OP => med_ctrl_op(1*16-1 downto 0*16),
+ STAT_DEBUG => med_stat_debug(1*64-1 downto 0*64),
+ CTRL_DEBUG => med_ctrl_debug(1*64-1 downto 0*64)
+);
+
+---------------------------------------------------------------------
+-- one normal port (SFP19)
+---------------------------------------------------------------------
+THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_gbe
+generic map(
+ SERDES_NUM => 0,
+ EXT_CLOCK => c_YES,
+ USE_200_MHZ => USE_200_MHZ
+)
+port map(
+ CLK => clk_in,
+ SYSCLK => clk_100,
+ RESET => reset_i,
+ CLEAR => reset_i_q,
+ CLK_EN => clk_en,
+ MED_DATA_IN => med_data_out(2*16-1 downto 1*16),
+ MED_PACKET_NUM_IN => med_packet_num_out(2*3-1 downto 1*3),
+ MED_DATAREADY_IN => med_dataready_out(1),
+ MED_READ_OUT => med_read_in(1),
+ MED_DATA_OUT => med_data_in(2*16-1 downto 1*16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(2*3-1 downto 1*3),
+ MED_DATAREADY_OUT => med_dataready_in(1),
+ MED_READ_IN => med_read_out(1),
+ REFCLK2CORE_OUT => clk_in,
+ SD_RXD_P_IN => SFP_RXP(19),
+ SD_RXD_N_IN => SFP_RXN(19),
+ SD_TXD_P_OUT => SFP_TXP(19),
+ SD_TXD_N_OUT => SFP_TXN(19),
+ SD_REFCLK_P_IN => SFP_REFCLKP(19),
+ SD_REFCLK_N_IN => SFP_REFCLKN(19),
+ SD_PRSNT_N_IN => buf_SFP_MOD0(19),
+ SD_LOS_IN => buf_SFP_LOS(19),
+ SD_TXDIS_OUT => SFP_DIS(19),
+ STAT_OP => med_stat_op(2*16-1 downto 1*16),
+ CTRL_OP => med_ctrl_op(2*16-1 downto 1*16),
+ STAT_DEBUG => med_stat_debug(2*64-1 downto 1*64),
+ CTRL_DEBUG => med_ctrl_debug(2*64-1 downto 1*64)
+);
+
+---------------------------------------------------------------------
+-- Connection between both FPGAs on HUB2 PCB
+---------------------------------------------------------------------
+THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC
+port map(
+ CLK => clk_100,
+ CLK_EN => clk_en,
+ RESET => reset_i,
+ --Internal Connection
+ MED_DATA_IN => med_data_out(3*16-1 downto 2*16),
+ MED_PACKET_NUM_IN => med_packet_num_out(3*3-1 downto 2*3),
+ MED_DATAREADY_IN => med_dataready_out(2),
+ MED_READ_OUT => med_read_in(2),
+ MED_DATA_OUT => med_data_in(3*16-1 downto 2*16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(3*3-1 downto 2*3),
+ MED_DATAREADY_OUT => med_dataready_in(2),
+ MED_READ_IN => med_read_out(2),
+ DATA_OUT => F2_TO_F1(31 downto 16),
+ DATA_VALID_OUT => F2_TO_F1(15),
+ DATA_CTRL_OUT => F2_TO_F1(14),
+ DATA_CLK_OUT => F2_TO_F1(1),
+ DATA_IN => F1_TO_F2(31 downto 16),
+ DATA_VALID_IN => F1_TO_F2(15),
+ DATA_CTRL_IN => F1_TO_F2(14),
+ DATA_CLK_IN => CLK_F1_TO_F2,
+ STAT_OP => med_stat_op(3*16-1 downto 2*16),
+ CTRL_OP => med_ctrl_op(3*16-1 downto 2*16),
+ STAT_DEBUG => med_stat_debug(3*64-1 downto 2*64)
+);
+---------------------------------------------------------------------
+-- Uplink port (SFP20)
+---------------------------------------------------------------------
+THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_gbe
+generic map(
+ SERDES_NUM => 0,
+ USE_200_MHZ => USE_200_MHZ
+)
+port map(
+ CLK => clk_in,
+ SYSCLK => clk_100,
+ RESET => reset_i,
+ CLEAR => reset_i_q,
+ CLK_EN => clk_en,
+ MED_DATA_IN => med_data_out(4*16-1 downto 3*16),
+ MED_PACKET_NUM_IN => med_packet_num_out(4*3-1 downto 3*3),
+ MED_DATAREADY_IN => med_dataready_out(3),
+ MED_READ_OUT => med_read_in(3),
+ MED_DATA_OUT => med_data_in(4*16-1 downto 3*16),
+ MED_PACKET_NUM_OUT => med_packet_num_in(4*3-1 downto 3*3),
+ MED_DATAREADY_OUT => med_dataready_in(3),
+ MED_READ_IN => med_read_out(3),
+ REFCLK2CORE_OUT => open,
+ SD_RXD_P_IN => SFP_RXP(20),
+ SD_RXD_N_IN => SFP_RXN(20),
+ SD_TXD_P_OUT => SFP_TXP(20),
+ SD_TXD_N_OUT => SFP_TXN(20),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => buf_SFP_MOD0(20),
+ SD_LOS_IN => buf_SFP_LOS(20),
+ SD_TXDIS_OUT => SFP_DIS(20),
+ STAT_OP => med_stat_op(4*16-1 downto 3*16),
+ CTRL_OP => med_ctrl_op(4*16-1 downto 3*16),
+ STAT_DEBUG => med_stat_debug(4*64-1 downto 3*64),
+ CTRL_DEBUG => med_ctrl_debug(4*64-1 downto 3*64)
+);
+
+med_ctrl_debug <= (others => '0');
+
+---------------------------------------------------------------------
+-- The Hub
+---------------------------------------------------------------------
+gen_normal_hub : if USE_ETHERNET = c_NO generate
+THE_HUB: trb_net16_hub_base
+generic map(
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ MII_NUMBER => mii,
+ MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1),
+ MII_IS_DOWNLINK => (others => 1),
+ INT_NUMBER => 0,
+ INT_CHANNELS => (0,1,3,3,3,3,3,3),
+ INIT_ENDPOINT_ID => x"0002",
+ USE_ONEWIRE => c_MONITOR,
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
+)
+port map(
+ CLK => clk_100,
+ RESET => reset_i,
+ CLK_EN => CLK_EN,
+ --Media interfacces
+ MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0),
+ MED_DATA_OUT => med_data_out(mii*16-1 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0),
+ MED_READ_IN => med_read_in(mii-1 downto 0),
+ MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0),
+ MED_DATA_IN => med_data_in(mii*16-1 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0),
+ MED_READ_OUT => med_read_out(mii-1 downto 0),
+ MED_STAT_OP => med_stat_op(mii*16-1 downto 0),
+ MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0),
+ INT_INIT_READ_IN => (others => '0'),
+ INT_INIT_DATAREADY_IN => (others => '0'),
+ INT_INIT_DATA_IN => (others => '0'),
+ INT_INIT_PACKET_NUM_IN => (others => '0'),
+ INT_REPLY_READ_IN => (others => '0'),
+ INT_REPLY_DATAREADY_IN => (others => '0'),
+ INT_REPLY_DATA_IN => (others => '0'),
+ INT_REPLY_PACKET_NUM_IN => (others => '0'),
+ ONEWIRE => open,
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ --Status ports (for debugging)
+ MPLEX_CTRL => (others => '0'),
+ CTRL_DEBUG => (others => '0'),
+ STAT_DEBUG => buf_test
+);
+
+TEST_2 <= (others => '0');
+
+--REGISTER_IT_PROC: process( buf_test(31) )
+--begin
+-- if rising_edge( buf_test(31) ) then
+-- TEST_2(30 downto 0) <= buf_test(30 downto 0);
+-- end if;
+--end process REGISTER_IT_PROC;
+--
+--TEST_2(31) <= buf_test(31);
+
+end generate;
+
+gen_ethernet_hub : if USE_ETHERNET = c_YES generate
+THE_HUB: trb_net16_hub_streaming_port
+generic map(
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+ IBUF_SECURE_MODE => c_YES,
+ INIT_ADDRESS => x"affe",
+-- MII_NUMBER => mii,
+-- MII_IS_UPLINK => ((mii-1) => 1, others => 0),
+-- MII_IS_DOWNLINK => ((mii-1) => 0, others => 1),
+-- 4 = SFP17 (GbE)
+-- 3 = SFP20 (TRBnet)
+-- 2 = LVDS (TRBnet)
+-- 1 = SFP19 (TRBnet)
+-- 0 = SFP18 (TRBnet)
+ MII_NUMBER => mii,
+ MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1),
+ MII_IS_DOWNLINK => (others => 1),
+ USE_ONEWIRE => c_MONITOR,
+ HARDWARE_VERSION => x"62210000", -- gk 26.05.10
+ INIT_ENDPOINT_ID => x"0002",
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
+)
+port map(
+ CLK => clk_100,
+ RESET => reset_i,
+ CLK_EN => clk_en,
+ --Media interfacces
+ MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0),
+ MED_DATA_OUT => med_data_out(mii*16-1 downto 0),
+ MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0),
+ MED_READ_IN => med_read_in(mii-1 downto 0),
+ MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0),
+ MED_DATA_IN => med_data_in(mii*16-1 downto 0),
+ MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0),
+ MED_READ_OUT => med_read_out(mii-1 downto 0),
+ MED_STAT_OP => med_stat_op(mii*16-1 downto 0),
+ MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0),
+ --Event information coming from CTSCTS_READOUT_TYPE_OUT
+ CTS_NUMBER_OUT => cts_number,
+ CTS_CODE_OUT => cts_code,
+ CTS_INFORMATION_OUT => cts_information,
+ CTS_READOUT_TYPE_OUT => cts_readout_type,
+ CTS_START_READOUT_OUT => cts_start_readout,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN => cts_data,
+ CTS_DATAREADY_IN => cts_dataready,
+ CTS_READOUT_FINISHED_IN => cts_readout_finished,
+ CTS_READ_OUT => cts_read,
+ CTS_LENGTH_IN => cts_length,
+ CTS_STATUS_BITS_IN => cts_status_bits,
+ -- Data from Frontends
+ FEE_DATA_OUT => fee_data,
+ FEE_DATAREADY_OUT => fee_dataready,
+ FEE_READ_IN => fee_read,
+ FEE_STATUS_BITS_OUT => fee_status_bits,
+ FEE_BUSY_OUT => fee_busy,
+ MY_ADDRESS_IN => my_address,
+ COMMON_STAT_REGS => open,
+ COMMON_CTRL_REGS => open,
+ ONEWIRE => open,
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
+ MY_ADDRESS_OUT => my_address,
+ REGIO_ADDR_OUT => regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
+ REGIO_DATA_OUT => regio_data_out,
+ REGIO_DATA_IN => regio_data_in,
+ REGIO_DATAREADY_IN => regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_timeout_out,
+ --Fixed status and control ports
+ MPLEX_CTRL => (others => '0'),
+ STAT_DEBUG => open, --buf_test,
+ CTRL_DEBUG => (others => '0')
+);
+
+---------------------------------------------------------------------
+-- The GbE machine for blasting out data from TRBnet
+---------------------------------------------------------------------
+GBE: trb_net16_gbe_buf
+generic map(
+ DO_SIMULATION => 0,
+ USE_125MHZ_EXTCLK => 1
+)
+port map(
+ CLK => clk_100,
+ TEST_CLK => test_clk,
+ CLK_125_TX_IN => '0',
+ CLK_125_RX_IN => '0',
+ RESET => reset_i,
+ GSR_N => gsr_n,
+ -- Debug
+ STAGE_STAT_REGS_OUT => stage_stat_regs, -- should be come STATUS or similar
+ STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE!
+ -- gk 22.04.10 not used any more, ip_configurator moved inside
+ -- configuration interface
+ IP_CFG_START_IN => stage_ctrl_regs(15),
+ IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8),
+ IP_CFG_DONE_OUT => open,
+ IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr,
+ IP_CFG_MEM_DATA_IN => ip_cfg_mem_data,
+ IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk,
+ MR_RESET_IN => stage_ctrl_regs(3),
+ MR_MODE_IN => stage_ctrl_regs(1),
+ MR_RESTART_IN => stage_ctrl_regs(0),
+ -- gk 29.03.10
+ -- interface to ip_configurator memory
+ SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0),
+ SLV_READ_IN => mb_ip_mem_read,
+ SLV_WRITE_IN => mb_ip_mem_write,
+ SLV_BUSY_OUT => open,
+ SLV_ACK_OUT => mb_ip_mem_ack,
+ SLV_DATA_IN => mb_ip_mem_data_wr,
+ SLV_DATA_OUT => mb_ip_mem_data_rd,
+ -- gk 26.04.10
+ -- gk 22.04.10
+ -- registers setup interface
+ BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0),
+ BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs,
+ BUS_DATA_OUT => gbe_stp_reg_data_rd,
+ BUS_WRITE_EN_IN => gbe_stp_reg_write,
+ BUS_READ_EN_IN => gbe_stp_reg_read,
+ BUS_ACK_OUT => gbe_stp_reg_ack,
+ -- gk 23.04.10
+ LED_PACKET_SENT_OUT => buf_SFP_LED_ORANGE(17),
+ LED_AN_DONE_N_OUT => buf_SFP_LED_GREEN(17),
+ -- CTS interface
+ CTS_NUMBER_IN => cts_number,
+ CTS_CODE_IN => cts_code,
+ CTS_INFORMATION_IN => cts_information,
+ CTS_READOUT_TYPE_IN => cts_readout_type,
+ CTS_START_READOUT_IN => cts_start_readout,
+ CTS_DATA_OUT => cts_data,
+ CTS_DATAREADY_OUT => cts_dataready,
+ CTS_READOUT_FINISHED_OUT => cts_readout_finished,
+ CTS_READ_IN => cts_read,
+ CTS_LENGTH_OUT => cts_length,
+ CTS_ERROR_PATTERN_OUT => cts_status_bits,
+ -- Data payload interface
+ FEE_DATA_IN => fee_data,
+ FEE_DATAREADY_IN => fee_dataready,
+ FEE_READ_OUT => fee_read,
+ FEE_STATUS_BITS_IN => fee_status_bits,
+ FEE_BUSY_IN => fee_busy,
+ --SFP Connection
+ SFP_RXD_P_IN => SFP_RXP(17),
+ SFP_RXD_N_IN => SFP_RXN(17),
+ SFP_TXD_P_OUT => SFP_TXP(17),
+ SFP_TXD_N_OUT => SFP_TXN(17),
+ SFP_REFCLK_P_IN => SFP_REFCLKP(17),
+ SFP_REFCLK_N_IN => SFP_REFCLKN(17),
+ SFP_PRSNT_N_IN => buf_SFP_MOD0(17), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SFP_LOS_IN => buf_SFP_LOS(17), -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SFP_TXDIS_OUT => SFP_DIS(17), -- SFP disable
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- PacketConstructor interface
+ IG_CTS_CTR_TST => open,
+ IG_REM_CTR_TST => open,
+ IG_BSM_LOAD_TST => open,
+ IG_BSM_SAVE_TST => open,
+ IG_DATA_TST(15 downto 8) => open,
+ IG_DATA_TST(7 downto 0) => buf_test(23 downto 16), --open,
+ IG_WCNT_TST => open,
+ IG_RCNT_TST => open,
+ IG_RD_EN_TST => buf_test(5), --open,
+ IG_WR_EN_TST => buf_test(6), --open,
+ IG_EMPTY_TST => open,
+ IG_AEMPTY_TST => buf_test(7), --open,
+ IG_FULL_TST => open,
+ IG_AFULL_TST => buf_test(8), --open,
+ PC_WR_EN_TST => buf_test(13), --open,
+ PC_DATA_TST => buf_test(31 downto 24), --open,
+ PC_READY_TST => buf_test(11), --open,
+ PC_START_OF_SUB_TST => buf_test(9), --open,
+ PC_END_OF_DATA_TST => buf_test(10), --open,
+ PC_SUB_SIZE_TST => open,
+ PC_TRIG_NR_TST => open,
+ PC_PADDING_TST => buf_test(12), --open,
+ PC_DECODING_TST => open,
+ PC_EVENT_ID_TST => open,
+ PC_QUEUE_DEC_TST => open,
+ PC_BSM_CONSTR_TST => open,
+ PC_BSM_LOAD_TST => open,
+ PC_BSM_SAVE_TST => open,
+ PC_ALL_CTR_TST => open,
+ PC_SUB_CTR_TST => open,
+ PC_SHF_EMPTY_TST => open,
+ PC_SHF_FULL_TST => open,
+ PC_DF_EMPTY_TST => open,
+ PC_DF_FULL_TST => open,
+ PC_BYTES_LOADED_TST => open,
+ PC_SIZE_LEFT_TST => open,
+ PC_SUB_SIZE_TO_SAVE_TST => open,
+ PC_SUB_SIZE_LOADED_TST => open,
+ PC_SUB_BYTES_LOADED_TST => open,
+ PC_QUEUE_SIZE_TST => open,
+ PC_ACT_QUEUE_SIZE_TST => open,
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameConstructor interface
+ FC_WR_EN_TST => open, --buf_test(15),
+ FC_DATA_TST => open,
+ FC_H_READY_TST => open, --buf_test(18), --open,
+ FC_READY_TST => buf_test(14), --open,
+ FC_IP_SIZE_TST => open,
+ FC_UDP_SIZE_TST => open,
+ FC_IDENT_TST => open,
+ FC_FLAGS_OFFSET_TST => open,
+ FC_SOD_TST => open, --buf_test(16), --open,
+ FC_EOD_TST => open, --buf_test(17), --open,
+ FC_BSM_CONSTR_TST(7 downto 3) => open,
+ FC_BSM_CONSTR_TST(2 downto 0) => open, --buf_test(28 downto 26), --open,
+ FC_BSM_TRANS_TST(3) => open,
+ FC_BSM_TRANS_TST(2 downto 0) => open, --buf_test(31 downto 29), --open,
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- FrameTransmitter interface
+ FT_DATA_TST(7 downto 3) => open,
+ FT_DATA_TST(2 downto 0) => open,
+ FT_TX_EMPTY_TST => open, --buf_test(19), --open,
+ FT_START_OF_PACKET_TST => open, --buf_test(20), --open,
+ FT_BSM_INIT_TST => open,
+ FT_BSM_MAC_TST => open,
+ FT_BSM_TRANS_TST => open,
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- MAC interface
+ MAC_HADDR_TST => open,
+ MAC_HDATA_TST => open,
+ MAC_HCS_TST => open,
+ MAC_HWRITE_TST => open,
+ MAC_HREAD_TST => open,
+ MAC_HREADY_TST => open,
+ MAC_HDATA_EN_TST => open,
+ MAC_FIFOAVAIL_TST => open, --buf_test(23), --open,
+ MAC_FIFOEOF_TST => open, --buf_test(24), --open,
+ MAC_FIFOEMPTY_TST => open, --buf_test(25), --open,
+ MAC_TX_READ_TST => open, --buf_test(21), --open,
+ MAC_TX_DONE_TST => open, --buf_test(22), --open,
+ -------------------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------------------
+ -- pcs and serdes
+ PCS_AN_LP_ABILITY_TST => open,
+ PCS_AN_COMPLETE_TST => open,
+ PCS_AN_PAGE_RX_TST => open,
+ -- debug ports
+ ANALYZER_DEBUG_OUT => analyzer_debug --open
+);
+
+---------------------------------------------------------------------
+-- LogicAnalyzer signals
+---------------------------------------------------------------------
+
+--buf_test(31 downto 0) <= (others => '0');
+
+buf_test(15) <= clk_100;
+
+buf_test(4) <= fee_busy;
+buf_test(3) <= fee_read;
+buf_test(2) <= fee_dataready;
+buf_test(1) <= cts_readout_finished;
+buf_test(0) <= cts_start_readout;
+
+-- output to pads
+--TEST_2 <= buf_test;
+REGISTER_IT_PROC: process( buf_test(15) )
+begin
+ if rising_edge( buf_test(15) ) then
+ TEST_2(31 downto 16) <= buf_test(31 downto 16);
+ TEST_2(14 downto 0) <= buf_test(14 downto 0);
+ end if;
+end process REGISTER_IT_PROC;
+
+TEST_2(15) <= buf_test(15);
+
+end generate;
+
+---------------------------------------------------------------------
+-- The Bus Handler for all Slow Control Activities
+---------------------------------------------------------------------
+-- reserved address space C000 - FFFF
+THE_BUS_HANDLER: trb_net16_regio_bus_handler
+generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => ( 0 => x"8000", 1 => x"8200", 2 => x"8100", 3=> x"8300", others => x"0000" ), -- gk 22.04.10
+ PORT_ADDR_MASK => ( 0 => 0, 1 => 0, 2 => 8, 3 => 8, others => 0) -- gk 22.04.10
+)
+port map(
+ CLK => clk_100,
+ RESET => reset_i,
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+ -- my registers
+ -- first one - control
+ BUS_ADDR_OUT(1*16-1 downto 0*16) => ctrl_reg_addr,
+ BUS_DATA_OUT(1*32-1 downto 0*32) => mb_ctrl_reg_data_wr,
+ BUS_READ_ENABLE_OUT(0) => mb_ctrl_reg_read,
+ BUS_WRITE_ENABLE_OUT(0) => mb_ctrl_reg_write,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(1*32-1 downto 0*32) => mb_ctrl_reg_data_rd,
+ BUS_DATAREADY_IN(0) => mb_ctrl_reg_ack,
+ BUS_WRITE_ACK_IN(0) => mb_ctrl_reg_ack,
+ BUS_NO_MORE_DATA_IN(0) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ -- second one - status
+ BUS_ADDR_OUT(2*16-1 downto 1*16) => open,
+ BUS_DATA_OUT(2*32-1 downto 1*32) => mb_stat_reg_data_wr,
+ BUS_READ_ENABLE_OUT(1) => mb_stat_reg_read,
+ BUS_WRITE_ENABLE_OUT(1) => mb_stat_reg_write,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(2*32-1 downto 1*32) => mb_stat_reg_data_rd,
+ BUS_DATAREADY_IN(1) => mb_stat_reg_ack,
+ BUS_WRITE_ACK_IN(1) => mb_stat_reg_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ -- third one - IP config memory
+ BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr,
+ BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr,
+ BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read,
+ BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd,
+ BUS_DATAREADY_IN(2) => mb_ip_mem_ack,
+ BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack,
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+
+ -- gk 22.04.10
+ -- gbe setup
+ BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr,
+ BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr,
+ BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read,
+ BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd,
+ BUS_DATAREADY_IN(3) => gbe_stp_reg_ack,
+ BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+ ----
+ STAT_DEBUG => open
+);
+
+---------------------------------------------------------------------
+-- MB CTRL REGISTER
+---------------------------------------------------------------------
+MB_CTRL_REGISTER : slv_register
+port map(
+ CLK_IN => clk_100,
+ RESET_IN => reset_i,
+ BUSY_IN => '0',
+ -- Slave bus
+ SLV_READ_IN => mb_ctrl_reg_read,
+ SLV_WRITE_IN => mb_ctrl_reg_write,
+ SLV_BUSY_OUT => open,
+ SLV_ACK_OUT => mb_ctrl_reg_ack,
+ SLV_DATA_IN => mb_ctrl_reg_data_wr,
+ SLV_DATA_OUT => mb_ctrl_reg_data_rd,
+ -- I/O to the backend
+ REG_DATA_IN => stage_ctrl_regs,
+ REG_DATA_OUT => stage_ctrl_regs,
+ -- Status lines
+ STAT => open
+);
+
+-- gk 26.04.10
+-- gk 22.04.10 register to manage gbe setup registers
+-- GBE_SETUP_REGISTER : slv_register
+-- port map(
+-- CLK => clk_100,
+-- RESET => reset_i,
+-- BUSY_IN => '0',
+-- -- Slave bus
+-- SLV_READ_IN => gbe_stp_reg_read,
+-- SLV_WRITE_IN => gbe_stp_reg_write,
+-- SLV_BUSY_OUT => open,
+-- SLV_ACK_OUT => gbe_stp_reg_ack,
+-- SLV_DATA_IN => gbe_stp_reg_data_wr,
+-- SLV_DATA_OUT => gbe_stp_reg_data_rd,
+-- -- I/O to the backend
+-- REG_DATA_IN => gbe_stp_data,
+-- REG_DATA_OUT => gbe_stp_data,
+-- -- Status lines
+-- STAT => open
+-- );
+
+---------------------------------------------------------------------
+-- MB STAT REGISTER
+---------------------------------------------------------------------
+MB_STAT_REGISTER : slv_register
+port map(
+ CLK_IN => clk_100,
+ RESET_IN => reset_i,
+ BUSY_IN => '0',
+ -- Slave bus
+ SLV_READ_IN => mb_stat_reg_read,
+ SLV_WRITE_IN => mb_stat_reg_write,
+ SLV_BUSY_OUT => open,
+ SLV_ACK_OUT => mb_stat_reg_ack,
+ SLV_DATA_IN => mb_stat_reg_data_wr,
+ SLV_DATA_OUT => mb_stat_reg_data_rd,
+ -- I/O to the backend
+ REG_DATA_IN => stage_stat_regs,
+ REG_DATA_OUT => open,
+ -- Status lines
+ STAT => open
+);
+
+-- gk 29.03.10 component moved to gbe_buf
+---------------------------------------------------------------------
+-- MB IP CONFIG MEMORY
+---------------------------------------------------------------------
+-- MB_IP_CONFIG: slv_mac_memory
+-- port map(
+-- CLK => clk_100,
+-- RESET => reset_i,
+-- BUSY_IN => '0',
+-- -- Slave bus
+-- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0),
+-- SLV_READ_IN => mb_ip_mem_read,
+-- SLV_WRITE_IN => mb_ip_mem_write,
+-- SLV_BUSY_OUT => open,
+-- SLV_ACK_OUT => mb_ip_mem_ack,
+-- SLV_DATA_IN => mb_ip_mem_data_wr,
+-- SLV_DATA_OUT => mb_ip_mem_data_rd,
+-- -- I/O to the backend
+-- MEM_CLK_IN => ip_cfg_mem_clk,
+-- MEM_ADDR_IN => ip_cfg_mem_addr,
+-- MEM_DATA_OUT => ip_cfg_mem_data,
+-- -- Status lines
+-- STAT => open
+-- );
+
+---------------------------------------------------------------------
+-- Funny LEDs ;-)
+---------------------------------------------------------------------
+buf_SFP_LED_ORANGE(18) <= not (med_stat_op(10) or med_stat_op(11));
+buf_SFP_LED_GREEN(18) <= not med_stat_op(9);
+
+buf_SFP_LED_ORANGE(19) <= not (med_stat_op(10+16) or med_stat_op(11+16));
+buf_SFP_LED_GREEN(19) <= not med_stat_op(9+16);
+
+buf_SFP_LED_ORANGE(20) <= not (med_stat_op(10+48) or med_stat_op(11+48));
+buf_SFP_LED_GREEN(20) <= not med_stat_op(9+48);
+
+-- gk 24.04.10
+--buf_SFP_LED_ORANGE(17) <= '0';
+--buf_SFP_LED_GREEN(17) <= '1';
+
+
+THE_LED_PROC: process( clk_100 )
+begin
+ if( rising_edge(clk_100) ) then
+ SFP_LED_GREEN <= buf_SFP_LED_GREEN;
+ SFP_LED_ORANGE <= buf_SFP_LED_ORANGE;
+ end if;
+end process THE_LED_PROC;
+
+---------------------------------------------------------------------
+--Debugging
+---------------------------------------------------------------------
+
+
+end architecture;
+=======
+--Port 19&20 is uplink, Port 18 is downlinks, 17 is reserved for Ethernet\r
+\r
+--the hub logic reports\r
+--sfp 18 = port 0\r
+--sfp 19 = port 1 Slowcontrol\r
+--lvds = port 2 to FPGA1\r
+--sfp 20 = port 3 CTS\r
+\r
+LIBRARY ieee;\r
+use ieee.std_logic_1164.all;\r
+USE IEEE.numeric_std.ALL;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.version.all;\r
+\r
+\r
+entity hub2_fpga2 is\r
+generic( USE_ETHERNET : integer range c_NO to c_YES := c_YES;\r
+ USE_200_MHZ : integer range c_NO to c_YES := c_YES\r
+ );\r
+port(\r
+-- CLK_F2_TO_F1 : out std_logic; -- unused\r
+ CLK_F1_TO_F2 : in std_logic;\r
+-- ADDON_RESET : in std_logic; -- unused\r
+-- RESET_N : in std_logic; -- unused\r
+-- SUPPL_RESET_N : in std_logic; -- unused\r
+ --Connection to TRB\r
+-- ADO_LV : inout std_logic_vector(61 downto 0);\r
+-- ADO_TTL : inout std_logic_vector(45 downto 0);\r
+ --Connection to FPGA1\r
+ F1_TO_F2 : in std_logic_vector(31 downto 0);\r
+ F2_TO_F1 : out std_logic_vector(31 downto 0);\r
+ --Optical Links\r
+ SFP_TXP : out std_logic_vector(20 downto 17);\r
+ SFP_TXN : out std_logic_vector(20 downto 17);\r
+ SFP_RXP : in std_logic_vector(20 downto 17);\r
+ SFP_RXN : in std_logic_vector(20 downto 17);\r
+ SFP_REFCLKP : in std_logic_vector(20 downto 17);\r
+ SFP_REFCLKN : in std_logic_vector(20 downto 17);\r
+ SFP_LED_GREEN : out std_logic_vector(20 downto 17);\r
+ SFP_LED_ORANGE : out std_logic_vector(20 downto 17);\r
+ SFP_MOD0 : in std_logic_vector(20 downto 17);\r
+ SFP_LOS : in std_logic_vector(20 downto 17);\r
+ SFP_DIS : out std_logic_vector(20 downto 17);\r
+ --Other\r
+ ONEWIRE_MONITOR_IN : in std_logic;\r
+ --Debugging\r
+ TEST_2 : out std_logic_vector(31 downto 0)\r
+);\r
+\r
+attribute syn_useioff : boolean;\r
+attribute syn_useioff of F1_TO_F2 : signal is true;\r
+attribute syn_useioff of F2_TO_F1 : signal is true;\r
+\r
+attribute syn_useioff of SFP_LED_GREEN : signal is false;\r
+attribute syn_useioff of SFP_LED_ORANGE : signal is false;\r
+\r
+end entity;\r
+\r
+architecture hub2_fpga2_arch of hub2_fpga2 is\r
+\r
+component slv_register is\r
+generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" );\r
+port( \r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+);\r
+end component;\r
+\r
+component trb_net16_gbe_buf is\r
+generic(\r
+ DO_SIMULATION : integer range 0 to 1 := 1;\r
+ USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+);\r
+port(\r
+ CLK : in std_logic;\r
+ TEST_CLK : in std_logic; -- only for simulation!\r
+ CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+ RESET : in std_logic;\r
+ GSR_N : in std_logic;\r
+ -- Debug\r
+ STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
+ STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
+ -- configuration interface\r
+ IP_CFG_START_IN : in std_logic;\r
+ IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
+ IP_CFG_DONE_OUT : out std_logic;\r
+ IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
+ IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
+ IP_CFG_MEM_CLK_OUT : out std_logic;\r
+ MR_RESET_IN : in std_logic;\r
+ MR_MODE_IN : in std_logic;\r
+ MR_RESTART_IN : in std_logic;\r
+ -- gk 29.03.10\r
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- gk 22.04.10\r
+ -- registers setup interface\r
+ BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
+ BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
+ BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
+ -- gk 23.04.10\r
+ LED_PACKET_SENT_OUT : out std_logic;\r
+ LED_AN_DONE_N_OUT : out std_logic;\r
+ -- CTS interface\r
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ CTS_START_READOUT_IN : in std_logic;\r
+ CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ CTS_DATAREADY_OUT : out std_logic;\r
+ CTS_READOUT_FINISHED_OUT : out std_logic;\r
+ CTS_READ_IN : in std_logic;\r
+ CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ -- Data payload interface\r
+ FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
+ FEE_DATAREADY_IN : in std_logic;\r
+ FEE_READ_OUT : out std_logic;\r
+ FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+ FEE_BUSY_IN : in std_logic;\r
+ --SFP Connection\r
+ SFP_RXD_P_IN : in std_logic;\r
+ SFP_RXD_N_IN : in std_logic;\r
+ SFP_TXD_P_OUT : out std_logic;\r
+ SFP_TXD_N_OUT : out std_logic;\r
+ SFP_REFCLK_P_IN : in std_logic;\r
+ SFP_REFCLK_N_IN : in std_logic;\r
+ SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- debug ports\r
+ ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+);\r
+end component;\r
+\r
+constant mii : integer := 4;\r
+\r
+-- Clocks and reset\r
+signal clk_in : std_logic; -- clock from SerDes reference output (100MHz or 200MHz)\r
+signal clk_100 : std_logic; -- 100MHz system clock\r
+signal clk_en : std_logic;\r
+signal reset_i_q : std_logic; -- fast async reset for SerDes\r
+signal pll_locked : std_logic;\r
+signal reset_counter : std_logic_vector(11 downto 0);\r
+signal next_reset : std_logic;\r
+signal reset_i : std_logic;\r
+signal make_reset_via_network_q : std_logic;\r
+signal make_reset_via_network : std_logic;\r
+signal gsr_n : std_logic;\r
+\r
+signal test_clk : std_logic; -- MUST BE ZERO!!!\r
+\r
+signal buf_SFP_LOS : std_logic_vector(20 downto 17);\r
+signal buf_SFP_MOD0 : std_logic_vector(20 downto 17);\r
+\r
+signal med_data_in : std_logic_vector(4*16-1 downto 0);\r
+signal med_data_out : std_logic_vector(4*16-1 downto 0);\r
+signal med_packet_num_in : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+signal med_packet_num_out : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+signal med_dataready_in : std_logic_vector(3 downto 0);\r
+signal med_dataready_out : std_logic_vector(3 downto 0);\r
+signal med_read_in : std_logic_vector(3 downto 0);\r
+signal med_read_out : std_logic_vector(3 downto 0);\r
+\r
+signal med_stat_op : std_logic_vector(4*16-1 downto 0);\r
+signal med_ctrl_op : std_logic_vector(4*16-1 downto 0);\r
+signal med_stat_debug : std_logic_vector(4*64-1 downto 0);\r
+signal med_ctrl_debug : std_logic_vector(4*64-1 downto 0);\r
+\r
+signal buf_SFP_LED_ORANGE : std_logic_vector(20 downto 17);\r
+signal buf_SFP_LED_GREEN : std_logic_vector(20 downto 17);\r
+\r
+signal cts_number : std_logic_vector(15 downto 0);\r
+signal cts_code : std_logic_vector(7 downto 0);\r
+signal cts_information : std_logic_vector(7 downto 0);\r
+signal cts_start_readout : std_logic;\r
+signal cts_readout_type : std_logic_vector(3 downto 0);\r
+signal cts_data : std_logic_vector(31 downto 0);\r
+signal cts_dataready : std_logic;\r
+signal cts_readout_finished : std_logic;\r
+signal cts_read : std_logic;\r
+signal cts_length : std_logic_vector(15 downto 0);\r
+signal cts_status_bits : std_logic_vector(31 downto 0);\r
+signal fee_data : std_logic_vector(15 downto 0);\r
+signal fee_dataready : std_logic;\r
+signal fee_read : std_logic;\r
+signal fee_status_bits : std_logic_vector(31 downto 0);\r
+signal fee_busy : std_logic;\r
+signal my_address : std_logic_vector(15 downto 0);\r
+\r
+signal stage_stat_regs : std_logic_vector (31 downto 0);\r
+signal stage_ctrl_regs : std_logic_vector (31 downto 0);\r
+\r
+--REGIO INTERFACE\r
+signal regio_addr_out : std_logic_vector(16-1 downto 0);\r
+signal regio_read_enable_out : std_logic;\r
+signal regio_write_enable_out : std_logic;\r
+signal regio_data_out : std_logic_vector(32-1 downto 0);\r
+signal regio_data_in : std_logic_vector(32-1 downto 0) := (others => '0');\r
+signal regio_dataready_in : std_logic := '0';\r
+signal regio_no_more_data_in : std_logic := '0';\r
+signal regio_write_ack_in : std_logic := '0';\r
+signal regio_unknown_addr_in : std_logic := '0';\r
+signal regio_timeout_out : std_logic;\r
+\r
+signal mb_ctrl_reg_data_wr : std_logic_vector(31 downto 0);\r
+signal mb_ctrl_reg_data_rd : std_logic_vector(31 downto 0);\r
+signal mb_ctrl_reg_read : std_logic;\r
+signal mb_ctrl_reg_write : std_logic;\r
+signal mb_ctrl_reg_ack : std_logic;\r
+\r
+signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0);\r
+signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0);\r
+signal mb_stat_reg_read : std_logic;\r
+signal mb_stat_reg_write : std_logic;\r
+signal mb_stat_reg_ack : std_logic;\r
+\r
+signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used\r
+signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0);\r
+signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0);\r
+signal mb_ip_mem_read : std_logic;\r
+signal mb_ip_mem_write : std_logic;\r
+signal mb_ip_mem_ack : std_logic;\r
+\r
+signal ip_cfg_mem_clk : std_logic;\r
+signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);\r
+signal ip_cfg_mem_data : std_logic_vector(31 downto 0);\r
+\r
+signal buf_test : std_logic_vector(31 downto 0);\r
+\r
+signal analyzer_debug : std_logic_vector(63 downto 0);\r
+\r
+-- gk 22.04.10\r
+signal ctrl_reg_addr : std_logic_vector(15 downto 0);\r
+signal gbe_stp_reg_addr : std_logic_vector(15 downto 0);\r
+signal gbe_stp_data : std_logic_vector(31 downto 0);\r
+signal gbe_stp_reg_ack : std_logic;\r
+signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0);\r
+signal gbe_stp_reg_read : std_logic;\r
+signal gbe_stp_reg_write : std_logic;\r
+signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0);\r
+\r
+\r
+begin\r
+\r
+---------------------------------------------------------------------\r
+-- Clock\r
+---------------------------------------------------------------------\r
+gen_no_pll : if USE_200_MHZ = c_NO generate\r
+THE_PLL : pll_in100_out100\r
+port map( CLK => clk_in,\r
+ CLKOP => clk_100,\r
+ LOCK => pll_locked\r
+ );\r
+end generate;\r
+\r
+gen_pll : if USE_200_MHZ = c_YES generate\r
+THE_PLL : pll_in200_out100\r
+port map( CLK => clk_in,\r
+ CLKOP => clk_100,\r
+ LOCK => pll_locked\r
+ );\r
+end generate;\r
+\r
+clk_en <= '1';\r
+test_clk <= '0';\r
+\r
+---------------------------------------------------------------------\r
+-- Reset process\r
+---------------------------------------------------------------------\r
+THE_RESET_COUNTER_PROC: process( pll_locked, clk_100 )\r
+begin\r
+ if( pll_locked = '0' ) then\r
+ -- asynchronous reset by PLL lock signal only\r
+ reset_counter <= (others => '0');\r
+ next_reset <= '1';\r
+ elsif( rising_edge(clk_100) ) then\r
+ if ( make_reset_via_network_q = '1' ) then\r
+ -- synchronous reset by network\r
+ reset_counter <= (others => '0');\r
+ next_reset <= '1';\r
+ elsif( reset_counter = x"EEE" ) then\r
+ reset_counter <= x"EEE";\r
+ next_reset <= '0';\r
+ else\r
+ reset_counter <= reset_counter + 1;\r
+ next_reset <= '1';\r
+ end if;\r
+ end if;\r
+end process THE_RESET_COUNTER_PROC;\r
+\r
+-- Fast aysnchronous reset for SerDes\r
+reset_i_q <= not pll_locked;\r
+\r
+gsr_n <= pll_locked;\r
+\r
+-- "normal" synchronous reset signal\r
+reset_i <= next_reset;\r
+\r
+-- reset by TRBnet (port 0 and 3 are uplinks)\r
+make_reset_via_network <= MED_STAT_OP(3*16+13) or MED_STAT_OP(0*16+13);\r
+\r
+THE_RESET_TRG_SYNC: signal_sync\r
+generic map( \r
+ DEPTH => 2,\r
+ WIDTH => 1 )\r
+port map( \r
+ RESET => '0',\r
+ D_IN(0) => make_reset_via_network,\r
+ CLK0 => clk_100,\r
+ CLK1 => clk_100,\r
+ D_OUT(0) => make_reset_via_network_q\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- Serdes\r
+---------------------------------------------------------------------\r
+\r
+-- Input synchronization\r
+THE_SFP_LOS_PROC: process( clk_100 )\r
+begin\r
+ if( rising_edge(clk_100) ) then\r
+ buf_SFP_LOS <= SFP_LOS;\r
+ buf_SFP_MOD0 <= SFP_MOD0;\r
+ end if;\r
+end process THE_SFP_LOS_PROC;\r
+\r
+---------------------------------------------------------------------\r
+-- one normal port (SFP18)\r
+---------------------------------------------------------------------\r
+THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe\r
+generic map( \r
+ SERDES_NUM => 0,\r
+ USE_200_MHZ => USE_200_MHZ \r
+)\r
+port map( \r
+ CLK => clk_in,\r
+ SYSCLK => clk_100,\r
+ RESET => reset_i,\r
+ CLEAR => reset_i_q,\r
+ CLK_EN => clk_en,\r
+ MED_DATA_IN => med_data_out(1*16-1 downto 0*16),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(1*3-1 downto 0*3),\r
+ MED_DATAREADY_IN => med_dataready_out(0),\r
+ MED_READ_OUT => med_read_in(0),\r
+ MED_DATA_OUT => med_data_in(1*16-1 downto 0*16),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(1*3-1 downto 0*3),\r
+ MED_DATAREADY_OUT => med_dataready_in(0),\r
+ MED_READ_IN => med_read_out(0),\r
+ REFCLK2CORE_OUT => open,\r
+ SD_RXD_P_IN => SFP_RXP(18),\r
+ SD_RXD_N_IN => SFP_RXN(18),\r
+ SD_TXD_P_OUT => SFP_TXP(18),\r
+ SD_TXD_N_OUT => SFP_TXN(18),\r
+ SD_REFCLK_P_IN => open,\r
+ SD_REFCLK_N_IN => open,\r
+ SD_PRSNT_N_IN => buf_SFP_MOD0(18),\r
+ SD_LOS_IN => buf_SFP_LOS(18),\r
+ SD_TXDIS_OUT => SFP_DIS(18),\r
+ STAT_OP => med_stat_op(1*16-1 downto 0*16),\r
+ CTRL_OP => med_ctrl_op(1*16-1 downto 0*16),\r
+ STAT_DEBUG => med_stat_debug(1*64-1 downto 0*64),\r
+ CTRL_DEBUG => med_ctrl_debug(1*64-1 downto 0*64)\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- one normal port (SFP19)\r
+---------------------------------------------------------------------\r
+THE_MEDIA_INTERFACE_2 : trb_net16_med_ecp_sfp_gbe\r
+generic map( \r
+ SERDES_NUM => 0,\r
+ EXT_CLOCK => c_YES,\r
+ USE_200_MHZ => USE_200_MHZ \r
+)\r
+port map( \r
+ CLK => clk_in,\r
+ SYSCLK => clk_100,\r
+ RESET => reset_i,\r
+ CLEAR => reset_i_q,\r
+ CLK_EN => clk_en,\r
+ MED_DATA_IN => med_data_out(2*16-1 downto 1*16),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(2*3-1 downto 1*3),\r
+ MED_DATAREADY_IN => med_dataready_out(1),\r
+ MED_READ_OUT => med_read_in(1),\r
+ MED_DATA_OUT => med_data_in(2*16-1 downto 1*16),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(2*3-1 downto 1*3),\r
+ MED_DATAREADY_OUT => med_dataready_in(1),\r
+ MED_READ_IN => med_read_out(1),\r
+ REFCLK2CORE_OUT => clk_in,\r
+ SD_RXD_P_IN => SFP_RXP(19),\r
+ SD_RXD_N_IN => SFP_RXN(19),\r
+ SD_TXD_P_OUT => SFP_TXP(19),\r
+ SD_TXD_N_OUT => SFP_TXN(19),\r
+ SD_REFCLK_P_IN => SFP_REFCLKP(19),\r
+ SD_REFCLK_N_IN => SFP_REFCLKN(19),\r
+ SD_PRSNT_N_IN => buf_SFP_MOD0(19),\r
+ SD_LOS_IN => buf_SFP_LOS(19),\r
+ SD_TXDIS_OUT => SFP_DIS(19),\r
+ STAT_OP => med_stat_op(2*16-1 downto 1*16),\r
+ CTRL_OP => med_ctrl_op(2*16-1 downto 1*16),\r
+ STAT_DEBUG => med_stat_debug(2*64-1 downto 1*64),\r
+ CTRL_DEBUG => med_ctrl_debug(2*64-1 downto 1*64)\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- Connection between both FPGAs on HUB2 PCB\r
+---------------------------------------------------------------------\r
+THE_MEDIA_INTERFACE_T : trb_net16_med_16_IC\r
+port map( \r
+ CLK => clk_100,\r
+ CLK_EN => clk_en,\r
+ RESET => reset_i,\r
+ --Internal Connection\r
+ MED_DATA_IN => med_data_out(3*16-1 downto 2*16),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(3*3-1 downto 2*3),\r
+ MED_DATAREADY_IN => med_dataready_out(2),\r
+ MED_READ_OUT => med_read_in(2),\r
+ MED_DATA_OUT => med_data_in(3*16-1 downto 2*16),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(3*3-1 downto 2*3),\r
+ MED_DATAREADY_OUT => med_dataready_in(2),\r
+ MED_READ_IN => med_read_out(2),\r
+ DATA_OUT => F2_TO_F1(31 downto 16),\r
+ DATA_VALID_OUT => F2_TO_F1(15),\r
+ DATA_CTRL_OUT => F2_TO_F1(14),\r
+ DATA_CLK_OUT => F2_TO_F1(1),\r
+ DATA_IN => F1_TO_F2(31 downto 16),\r
+ DATA_VALID_IN => F1_TO_F2(15),\r
+ DATA_CTRL_IN => F1_TO_F2(14),\r
+ DATA_CLK_IN => CLK_F1_TO_F2,\r
+ STAT_OP => med_stat_op(3*16-1 downto 2*16),\r
+ CTRL_OP => med_ctrl_op(3*16-1 downto 2*16),\r
+ STAT_DEBUG => med_stat_debug(3*64-1 downto 2*64)\r
+);\r
+---------------------------------------------------------------------\r
+-- Uplink port (SFP20)\r
+---------------------------------------------------------------------\r
+THE_MEDIA_INTERFACE_3 : trb_net16_med_ecp_sfp_gbe\r
+generic map( \r
+ SERDES_NUM => 0,\r
+ USE_200_MHZ => USE_200_MHZ \r
+)\r
+port map( \r
+ CLK => clk_in,\r
+ SYSCLK => clk_100,\r
+ RESET => reset_i,\r
+ CLEAR => reset_i_q,\r
+ CLK_EN => clk_en,\r
+ MED_DATA_IN => med_data_out(4*16-1 downto 3*16),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(4*3-1 downto 3*3),\r
+ MED_DATAREADY_IN => med_dataready_out(3),\r
+ MED_READ_OUT => med_read_in(3),\r
+ MED_DATA_OUT => med_data_in(4*16-1 downto 3*16),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(4*3-1 downto 3*3),\r
+ MED_DATAREADY_OUT => med_dataready_in(3),\r
+ MED_READ_IN => med_read_out(3),\r
+ REFCLK2CORE_OUT => open,\r
+ SD_RXD_P_IN => SFP_RXP(20),\r
+ SD_RXD_N_IN => SFP_RXN(20),\r
+ SD_TXD_P_OUT => SFP_TXP(20),\r
+ SD_TXD_N_OUT => SFP_TXN(20),\r
+ SD_REFCLK_P_IN => open,\r
+ SD_REFCLK_N_IN => open,\r
+ SD_PRSNT_N_IN => buf_SFP_MOD0(20),\r
+ SD_LOS_IN => buf_SFP_LOS(20),\r
+ SD_TXDIS_OUT => SFP_DIS(20),\r
+ STAT_OP => med_stat_op(4*16-1 downto 3*16),\r
+ CTRL_OP => med_ctrl_op(4*16-1 downto 3*16),\r
+ STAT_DEBUG => med_stat_debug(4*64-1 downto 3*64),\r
+ CTRL_DEBUG => med_ctrl_debug(4*64-1 downto 3*64)\r
+);\r
+\r
+med_ctrl_debug <= (others => '0');\r
+\r
+---------------------------------------------------------------------\r
+-- The Hub\r
+---------------------------------------------------------------------\r
+gen_normal_hub : if USE_ETHERNET = c_NO generate\r
+THE_HUB: trb_net16_hub_base\r
+generic map( \r
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),\r
+ IBUF_SECURE_MODE => c_YES,\r
+ MII_NUMBER => mii,\r
+ MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1),\r
+ MII_IS_DOWNLINK => (others => 1),\r
+ INT_NUMBER => 0,\r
+ INT_CHANNELS => (0,1,3,3,3,3,3,3),\r
+ INIT_ENDPOINT_ID => x"0002",\r
+ USE_ONEWIRE => c_MONITOR,\r
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))\r
+)\r
+port map( \r
+ CLK => clk_100,\r
+ RESET => reset_i,\r
+ CLK_EN => CLK_EN,\r
+ --Media interfacces\r
+ MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0),\r
+ MED_DATA_OUT => med_data_out(mii*16-1 downto 0),\r
+ MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0),\r
+ MED_READ_IN => med_read_in(mii-1 downto 0),\r
+ MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0),\r
+ MED_DATA_IN => med_data_in(mii*16-1 downto 0),\r
+ MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0),\r
+ MED_READ_OUT => med_read_out(mii-1 downto 0),\r
+ MED_STAT_OP => med_stat_op(mii*16-1 downto 0),\r
+ MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0),\r
+ INT_INIT_READ_IN => (others => '0'),\r
+ INT_INIT_DATAREADY_IN => (others => '0'),\r
+ INT_INIT_DATA_IN => (others => '0'),\r
+ INT_INIT_PACKET_NUM_IN => (others => '0'),\r
+ INT_REPLY_READ_IN => (others => '0'),\r
+ INT_REPLY_DATAREADY_IN => (others => '0'),\r
+ INT_REPLY_DATA_IN => (others => '0'),\r
+ INT_REPLY_PACKET_NUM_IN => (others => '0'),\r
+ ONEWIRE => open,\r
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,\r
+ --REGIO INTERFACE\r
+ REGIO_ADDR_OUT => regio_addr_out,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,\r
+ REGIO_DATA_OUT => regio_data_out,\r
+ REGIO_DATA_IN => regio_data_in,\r
+ REGIO_DATAREADY_IN => regio_dataready_in,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
+ REGIO_TIMEOUT_OUT => regio_timeout_out,\r
+ --Status ports (for debugging)\r
+ MPLEX_CTRL => (others => '0'),\r
+ CTRL_DEBUG => (others => '0'),\r
+ STAT_DEBUG => buf_test\r
+);\r
+\r
+TEST_2 <= (others => '0');\r
+\r
+--REGISTER_IT_PROC: process( buf_test(31) )\r
+--begin\r
+-- if rising_edge( buf_test(31) ) then\r
+-- TEST_2(30 downto 0) <= buf_test(30 downto 0); \r
+-- end if;\r
+--end process REGISTER_IT_PROC;\r
+--\r
+--TEST_2(31) <= buf_test(31);\r
+\r
+end generate;\r
+\r
+gen_ethernet_hub : if USE_ETHERNET = c_YES generate\r
+THE_HUB: trb_net16_hub_streaming_port\r
+generic map( \r
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),\r
+ IBUF_SECURE_MODE => c_YES,\r
+ INIT_ADDRESS => x"affe",\r
+-- MII_NUMBER => mii,\r
+-- MII_IS_UPLINK => ((mii-1) => 1, others => 0),\r
+-- MII_IS_DOWNLINK => ((mii-1) => 0, others => 1),\r
+-- 4 = SFP17 (GbE)\r
+-- 3 = SFP20 (TRBnet)\r
+-- 2 = LVDS (TRBnet)\r
+-- 1 = SFP19 (TRBnet)\r
+-- 0 = SFP18 (TRBnet)\r
+ MII_NUMBER => mii,\r
+ MII_IS_UPLINK => (0 => 1, 1 => 0, 2 => 0, 3 => 1, others => 1),\r
+ MII_IS_DOWNLINK => (others => 1),\r
+ USE_ONEWIRE => c_MONITOR,\r
+ HARDWARE_VERSION => x"62210000", -- gk 26.05.10\r
+ INIT_ENDPOINT_ID => x"0002",\r
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))\r
+)\r
+port map( \r
+ CLK => clk_100,\r
+ RESET => reset_i,\r
+ CLK_EN => clk_en,\r
+ --Media interfacces\r
+ MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0),\r
+ MED_DATA_OUT => med_data_out(mii*16-1 downto 0),\r
+ MED_PACKET_NUM_OUT => med_packet_num_out(mii*3-1 downto 0),\r
+ MED_READ_IN => med_read_in(mii-1 downto 0),\r
+ MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0),\r
+ MED_DATA_IN => med_data_in(mii*16-1 downto 0),\r
+ MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0),\r
+ MED_READ_OUT => med_read_out(mii-1 downto 0),\r
+ MED_STAT_OP => med_stat_op(mii*16-1 downto 0),\r
+ MED_CTRL_OP => med_ctrl_op(mii*16-1 downto 0),\r
+ --Event information coming from CTSCTS_READOUT_TYPE_OUT\r
+ CTS_NUMBER_OUT => cts_number,\r
+ CTS_CODE_OUT => cts_code,\r
+ CTS_INFORMATION_OUT => cts_information,\r
+ CTS_READOUT_TYPE_OUT => cts_readout_type,\r
+ CTS_START_READOUT_OUT => cts_start_readout,\r
+ --Information sent to CTS\r
+ --status data, equipped with DHDR\r
+ CTS_DATA_IN => cts_data,\r
+ CTS_DATAREADY_IN => cts_dataready,\r
+ CTS_READOUT_FINISHED_IN => cts_readout_finished,\r
+ CTS_READ_OUT => cts_read,\r
+ CTS_LENGTH_IN => cts_length,\r
+ CTS_STATUS_BITS_IN => cts_status_bits,\r
+ -- Data from Frontends\r
+ FEE_DATA_OUT => fee_data,\r
+ FEE_DATAREADY_OUT => fee_dataready,\r
+ FEE_READ_IN => fee_read,\r
+ FEE_STATUS_BITS_OUT => fee_status_bits,\r
+ FEE_BUSY_OUT => fee_busy,\r
+ MY_ADDRESS_IN => my_address,\r
+ COMMON_STAT_REGS => open,\r
+ COMMON_CTRL_REGS => open,\r
+ ONEWIRE => open,\r
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,\r
+ MY_ADDRESS_OUT => my_address,\r
+ REGIO_ADDR_OUT => regio_addr_out,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,\r
+ REGIO_DATA_OUT => regio_data_out,\r
+ REGIO_DATA_IN => regio_data_in,\r
+ REGIO_DATAREADY_IN => regio_dataready_in,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
+ REGIO_TIMEOUT_OUT => regio_timeout_out,\r
+ --Fixed status and control ports\r
+ MPLEX_CTRL => (others => '0'),\r
+ STAT_DEBUG => open, --buf_test,\r
+ CTRL_DEBUG => (others => '0')\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- The GbE machine for blasting out data from TRBnet\r
+---------------------------------------------------------------------\r
+\r
+GBE: trb_net16_gbe_buf\r
+generic map( \r
+ DO_SIMULATION => 0,\r
+ USE_125MHZ_EXTCLK => 1\r
+)\r
+port map( \r
+ CLK => clk_100,\r
+ TEST_CLK => test_clk,\r
+ CLK_125_IN => '0',\r
+ RESET => reset_i,\r
+ GSR_N => gsr_n,\r
+ -- Debug\r
+ STAGE_STAT_REGS_OUT => stage_stat_regs, -- should be come STATUS or similar\r
+ STAGE_CTRL_REGS_IN => stage_ctrl_regs, -- OBSELETE!\r
+ -- gk 22.04.10 not used any more, ip_configurator moved inside\r
+ -- configuration interface\r
+ IP_CFG_START_IN => stage_ctrl_regs(15),\r
+ IP_CFG_BANK_SEL_IN => stage_ctrl_regs(11 downto 8),\r
+ IP_CFG_DONE_OUT => open,\r
+ IP_CFG_MEM_ADDR_OUT => ip_cfg_mem_addr,\r
+ IP_CFG_MEM_DATA_IN => ip_cfg_mem_data,\r
+ IP_CFG_MEM_CLK_OUT => ip_cfg_mem_clk,\r
+ MR_RESET_IN => stage_ctrl_regs(3),\r
+ MR_MODE_IN => stage_ctrl_regs(1),\r
+ MR_RESTART_IN => stage_ctrl_regs(0),\r
+ -- gk 29.03.10\r
+ -- interface to ip_configurator memory\r
+ SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0),\r
+ SLV_READ_IN => mb_ip_mem_read,\r
+ SLV_WRITE_IN => mb_ip_mem_write,\r
+ SLV_BUSY_OUT => open,\r
+ SLV_ACK_OUT => mb_ip_mem_ack,\r
+ SLV_DATA_IN => mb_ip_mem_data_wr,\r
+ SLV_DATA_OUT => mb_ip_mem_data_rd,\r
+ -- gk 26.04.10\r
+ -- gk 22.04.10\r
+ -- registers setup interface\r
+ BUS_ADDR_IN => gbe_stp_reg_addr(7 downto 0), --ctrl_reg_addr(7 downto 0),\r
+ BUS_DATA_IN => gbe_stp_reg_data_wr, --stage_ctrl_regs,\r
+ BUS_DATA_OUT => gbe_stp_reg_data_rd,\r
+ BUS_WRITE_EN_IN => gbe_stp_reg_write,\r
+ BUS_READ_EN_IN => gbe_stp_reg_read,\r
+ BUS_ACK_OUT => gbe_stp_reg_ack,\r
+ -- gk 23.04.10\r
+ LED_PACKET_SENT_OUT => buf_SFP_LED_ORANGE(17),\r
+ LED_AN_DONE_N_OUT => buf_SFP_LED_GREEN(17),\r
+ -- CTS interface\r
+ CTS_NUMBER_IN => cts_number,\r
+ CTS_CODE_IN => cts_code,\r
+ CTS_INFORMATION_IN => cts_information,\r
+ CTS_READOUT_TYPE_IN => cts_readout_type,\r
+ CTS_START_READOUT_IN => cts_start_readout,\r
+ CTS_DATA_OUT => cts_data,\r
+ CTS_DATAREADY_OUT => cts_dataready,\r
+ CTS_READOUT_FINISHED_OUT => cts_readout_finished,\r
+ CTS_READ_IN => cts_read,\r
+ CTS_LENGTH_OUT => cts_length,\r
+ CTS_ERROR_PATTERN_OUT => cts_status_bits,\r
+ -- Data payload interface\r
+ FEE_DATA_IN => fee_data,\r
+ FEE_DATAREADY_IN => fee_dataready,\r
+ FEE_READ_OUT => fee_read,\r
+ FEE_STATUS_BITS_IN => fee_status_bits,\r
+ FEE_BUSY_IN => fee_busy,\r
+ --SFP Connection\r
+ SFP_RXD_P_IN => SFP_RXP(17),\r
+ SFP_RXD_N_IN => SFP_RXN(17),\r
+ SFP_TXD_P_OUT => SFP_TXP(17),\r
+ SFP_TXD_N_OUT => SFP_TXN(17),\r
+ SFP_REFCLK_P_IN => SFP_REFCLKP(17),\r
+ SFP_REFCLK_N_IN => SFP_REFCLKN(17),\r
+ SFP_PRSNT_N_IN => buf_SFP_MOD0(17), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SFP_LOS_IN => buf_SFP_LOS(17), -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SFP_TXDIS_OUT => SFP_DIS(17), -- SFP disable\r
+ ANALYZER_DEBUG_OUT => analyzer_debug --open\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- LogicAnalyzer signals\r
+---------------------------------------------------------------------\r
+\r
+--buf_test(31 downto 0) <= (others => '0');\r
+\r
+buf_test(15) <= clk_100;\r
+\r
+buf_test(4) <= fee_busy;\r
+buf_test(3) <= fee_read;\r
+buf_test(2) <= fee_dataready;\r
+buf_test(1) <= cts_readout_finished;\r
+buf_test(0) <= cts_start_readout;\r
+\r
+-- output to pads\r
+--TEST_2 <= buf_test;\r
+REGISTER_IT_PROC: process( buf_test(15) )\r
+begin\r
+ if rising_edge( buf_test(15) ) then\r
+ TEST_2(31 downto 16) <= buf_test(31 downto 16); \r
+ TEST_2(14 downto 0) <= buf_test(14 downto 0); \r
+ end if;\r
+end process REGISTER_IT_PROC;\r
+\r
+TEST_2(15) <= buf_test(15);\r
+\r
+end generate;\r
+\r
+---------------------------------------------------------------------\r
+-- The Bus Handler for all Slow Control Activities\r
+---------------------------------------------------------------------\r
+-- reserved address space C000 - FFFF\r
+THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
+generic map( \r
+ PORT_NUMBER => 4,\r
+ PORT_ADDRESSES => ( 0 => x"8000", 1 => x"8200", 2 => x"8100", 3=> x"8300", others => x"0000" ), -- gk 22.04.10 \r
+ PORT_ADDR_MASK => ( 0 => 0, 1 => 0, 2 => 8, 3 => 8, others => 0) -- gk 22.04.10\r
+)\r
+port map( \r
+ CLK => clk_100,\r
+ RESET => reset_i,\r
+ DAT_ADDR_IN => regio_addr_out,\r
+ DAT_DATA_IN => regio_data_out,\r
+ DAT_DATA_OUT => regio_data_in,\r
+ DAT_READ_ENABLE_IN => regio_read_enable_out,\r
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,\r
+ DAT_TIMEOUT_IN => regio_timeout_out,\r
+ DAT_DATAREADY_OUT => regio_dataready_in,\r
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,\r
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,\r
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,\r
+ -- my registers\r
+ -- first one - control\r
+ BUS_ADDR_OUT(1*16-1 downto 0*16) => ctrl_reg_addr,\r
+ BUS_DATA_OUT(1*32-1 downto 0*32) => mb_ctrl_reg_data_wr,\r
+ BUS_READ_ENABLE_OUT(0) => mb_ctrl_reg_read,\r
+ BUS_WRITE_ENABLE_OUT(0) => mb_ctrl_reg_write,\r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_DATA_IN(1*32-1 downto 0*32) => mb_ctrl_reg_data_rd,\r
+ BUS_DATAREADY_IN(0) => mb_ctrl_reg_ack,\r
+ BUS_WRITE_ACK_IN(0) => mb_ctrl_reg_ack,\r
+ BUS_NO_MORE_DATA_IN(0) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(0) => '0',\r
+ -- second one - status\r
+ BUS_ADDR_OUT(2*16-1 downto 1*16) => open,\r
+ BUS_DATA_OUT(2*32-1 downto 1*32) => mb_stat_reg_data_wr,\r
+ BUS_READ_ENABLE_OUT(1) => mb_stat_reg_read,\r
+ BUS_WRITE_ENABLE_OUT(1) => mb_stat_reg_write,\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_DATA_IN(2*32-1 downto 1*32) => mb_stat_reg_data_rd,\r
+ BUS_DATAREADY_IN(1) => mb_stat_reg_ack,\r
+ BUS_WRITE_ACK_IN(1) => mb_stat_reg_ack,\r
+ BUS_NO_MORE_DATA_IN(1) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ -- third one - IP config memory\r
+ BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr,\r
+ BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr,\r
+ BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read,\r
+ BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd,\r
+ BUS_DATAREADY_IN(2) => mb_ip_mem_ack,\r
+ BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack,\r
+ BUS_NO_MORE_DATA_IN(2) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(2) => '0',\r
+\r
+ -- gk 22.04.10\r
+ -- gbe setup\r
+ BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr,\r
+ BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr,\r
+ BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read,\r
+ BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write,\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+ BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd,\r
+ BUS_DATAREADY_IN(3) => gbe_stp_reg_ack,\r
+ BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack,\r
+ BUS_NO_MORE_DATA_IN(3) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+ ----\r
+ STAT_DEBUG => open\r
+);\r
+\r
+---------------------------------------------------------------------\r
+-- MB CTRL REGISTER\r
+---------------------------------------------------------------------\r
+MB_CTRL_REGISTER : slv_register\r
+port map( \r
+ CLK_IN => clk_100,\r
+ RESET_IN => reset_i,\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => mb_ctrl_reg_read,\r
+ SLV_WRITE_IN => mb_ctrl_reg_write,\r
+ SLV_BUSY_OUT => open,\r
+ SLV_ACK_OUT => mb_ctrl_reg_ack,\r
+ SLV_DATA_IN => mb_ctrl_reg_data_wr,\r
+ SLV_DATA_OUT => mb_ctrl_reg_data_rd,\r
+ -- I/O to the backend\r
+ REG_DATA_IN => stage_ctrl_regs,\r
+ REG_DATA_OUT => stage_ctrl_regs,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
+\r
+-- gk 26.04.10\r
+-- gk 22.04.10 register to manage gbe setup registers\r
+-- GBE_SETUP_REGISTER : slv_register\r
+-- port map( \r
+-- CLK => clk_100,\r
+-- RESET => reset_i,\r
+-- BUSY_IN => '0',\r
+-- -- Slave bus\r
+-- SLV_READ_IN => gbe_stp_reg_read,\r
+-- SLV_WRITE_IN => gbe_stp_reg_write,\r
+-- SLV_BUSY_OUT => open,\r
+-- SLV_ACK_OUT => gbe_stp_reg_ack,\r
+-- SLV_DATA_IN => gbe_stp_reg_data_wr,\r
+-- SLV_DATA_OUT => gbe_stp_reg_data_rd,\r
+-- -- I/O to the backend\r
+-- REG_DATA_IN => gbe_stp_data,\r
+-- REG_DATA_OUT => gbe_stp_data,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+\r
+---------------------------------------------------------------------\r
+-- MB STAT REGISTER\r
+---------------------------------------------------------------------\r
+MB_STAT_REGISTER : slv_register\r
+port map( \r
+ CLK_IN => clk_100,\r
+ RESET_IN => reset_i,\r
+ BUSY_IN => '0',\r
+ -- Slave bus\r
+ SLV_READ_IN => mb_stat_reg_read,\r
+ SLV_WRITE_IN => mb_stat_reg_write,\r
+ SLV_BUSY_OUT => open,\r
+ SLV_ACK_OUT => mb_stat_reg_ack,\r
+ SLV_DATA_IN => mb_stat_reg_data_wr,\r
+ SLV_DATA_OUT => mb_stat_reg_data_rd,\r
+ -- I/O to the backend\r
+ REG_DATA_IN => stage_stat_regs,\r
+ REG_DATA_OUT => open,\r
+ -- Status lines\r
+ STAT => open\r
+);\r
+\r
+-- gk 29.03.10 component moved to gbe_buf\r
+---------------------------------------------------------------------\r
+-- MB IP CONFIG MEMORY\r
+---------------------------------------------------------------------\r
+-- MB_IP_CONFIG: slv_mac_memory\r
+-- port map( \r
+-- CLK => clk_100,\r
+-- RESET => reset_i,\r
+-- BUSY_IN => '0',\r
+-- -- Slave bus\r
+-- SLV_ADDR_IN => mb_ip_mem_addr(7 downto 0),\r
+-- SLV_READ_IN => mb_ip_mem_read,\r
+-- SLV_WRITE_IN => mb_ip_mem_write,\r
+-- SLV_BUSY_OUT => open,\r
+-- SLV_ACK_OUT => mb_ip_mem_ack,\r
+-- SLV_DATA_IN => mb_ip_mem_data_wr,\r
+-- SLV_DATA_OUT => mb_ip_mem_data_rd,\r
+-- -- I/O to the backend\r
+-- MEM_CLK_IN => ip_cfg_mem_clk,\r
+-- MEM_ADDR_IN => ip_cfg_mem_addr,\r
+-- MEM_DATA_OUT => ip_cfg_mem_data,\r
+-- -- Status lines\r
+-- STAT => open\r
+-- );\r
+\r
+---------------------------------------------------------------------\r
+-- Funny LEDs ;-)\r
+---------------------------------------------------------------------\r
+buf_SFP_LED_ORANGE(18) <= not (med_stat_op(10) or med_stat_op(11));\r
+buf_SFP_LED_GREEN(18) <= not med_stat_op(9);\r
+\r
+buf_SFP_LED_ORANGE(19) <= not (med_stat_op(10+16) or med_stat_op(11+16));\r
+buf_SFP_LED_GREEN(19) <= not med_stat_op(9+16);\r
+\r
+buf_SFP_LED_ORANGE(20) <= not (med_stat_op(10+48) or med_stat_op(11+48));\r
+buf_SFP_LED_GREEN(20) <= not med_stat_op(9+48);\r
+\r
+-- gk 24.04.10\r
+--buf_SFP_LED_ORANGE(17) <= '0';\r
+--buf_SFP_LED_GREEN(17) <= '1';\r
+\r
+\r
+THE_LED_PROC: process( clk_100 )\r
+begin\r
+ if( rising_edge(clk_100) ) then\r
+ SFP_LED_GREEN <= buf_SFP_LED_GREEN;\r
+ SFP_LED_ORANGE <= buf_SFP_LED_ORANGE;\r
+ end if;\r
+end process THE_LED_PROC;\r
+\r
+---------------------------------------------------------------------\r
+--Debugging\r
+---------------------------------------------------------------------\r
+\r
+\r
+end architecture;>>>>>>> 1.20
jspc29 / trb2_hub.git / commitdiff