--- /dev/null
+#################################################################\r
+# Clock I/O\r
+#################################################################\r
+LOCATE COMP "CLK_SUPPL_PLL_RIGHT" SITE "Y28"; #was SUPPL_CLOCK1_P\r
+LOCATE COMP "CLK_SUPPL_PLL_LEFT" SITE "Y9"; #was SUPPL_CLOCK2_P\r
+LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P\r
+LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P"\r
+LOCATE COMP "CLK_CORE_PLL_LEFT" SITE "U6"; #was "CORE_CLOCK1_P"\r
+LOCATE COMP "CLK_CORE_PLL_RIGHT" SITE "V34"; #was "CORE_CLOCK2_P"\r
+LOCATE COMP "CLK_EXT_PCLK" SITE "U28"; #was "EXT_CLOCK0_P"\r
+LOCATE COMP "CLK_EXT_PLL_RIGHT" SITE "P30"; #was "EXT_CLOCK1_P"\r
+LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P"\r
+DEFINE PORT GROUP "CLK_group" "CLK*" ;\r
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+\r
+\r
+LOCATE COMP "TRIG_PLL" SITE "AJ34";\r
+LOCATE COMP "TRIG_RIGHT" SITE "P34";\r
+LOCATE COMP "TRIG_LEFT" SITE "T6";\r
+DEFINE PORT GROUP "TRIG_group" "TRIG*" ;\r
+IOBUF GROUP "TRIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+\r
+\r
+\r
+\r
+#################################################################\r
+# Backplane I/O\r
+#################################################################\r
+LOCATE COMP "BACK_GPIO_0" SITE "C26";\r
+LOCATE COMP "BACK_GPIO_1" SITE "D26";\r
+LOCATE COMP "BACK_GPIO_2" SITE "B27";\r
+LOCATE COMP "BACK_GPIO_3" SITE "C27";\r
+LOCATE COMP "BACK_GPIO_4" SITE "D27";\r
+LOCATE COMP "BACK_GPIO_5" SITE "E27";\r
+LOCATE COMP "BACK_GPIO_6" SITE "B28";\r
+LOCATE COMP "BACK_GPIO_7" SITE "A28";\r
+LOCATE COMP "BACK_GPIO_8" SITE "A26";\r
+LOCATE COMP "BACK_GPIO_9" SITE "A27";\r
+LOCATE COMP "BACK_GPIO_10" SITE "A29";\r
+LOCATE COMP "BACK_GPIO_11" SITE "A30";\r
+LOCATE COMP "BACK_GPIO_12" SITE "H26";\r
+LOCATE COMP "BACK_GPIO_13" SITE "H25";\r
+LOCATE COMP "BACK_GPIO_14" SITE "A31";\r
+LOCATE COMP "BACK_GPIO_15" SITE "B31";\r
+DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ;\r
+IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+\r
+LOCATE COMP "BACK_LVDS_0" SITE "V2";\r
+LOCATE COMP "BACK_LVDS_1" SITE "T4";\r
+# LOCATE COMP "BACK_LVDS_0_N" SITE "V1";\r
+# LOCATE COMP "BACK_LVDS_1_N" SITE "T3";\r
+DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ;\r
+IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25;\r
+\r
+LOCATE COMP "BACK_3V3_0" SITE "E11";\r
+LOCATE COMP "BACK_3V3_1" SITE "F12";\r
+LOCATE COMP "BACK_3V3_2" SITE "F10";\r
+LOCATE COMP "BACK_3V3_3" SITE "E10";\r
+DEFINE PORT GROUP "BACK_3V3_group" "BACK_3V3*" ;\r
+IOBUF GROUP "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN;\r
+\r
+#################################################################\r
+# AddOn Connector\r
+#################################################################\r
+# # LOCATE COMP "DQLL0_0_N" SITE "AA1";\r
+# # LOCATE COMP "DQLL0_1_N" SITE "AB1";\r
+# # LOCATE COMP "DQLL0_2_N" SITE "AA3";\r
+# # LOCATE COMP "DQLL0_3_N" SITE "AB5";\r
+# # LOCATE COMP "DQLL0_4_N" SITE "AA7";\r
+# # LOCATE COMP "DQLL1_0_N" SITE "Y1";\r
+# # LOCATE COMP "DQLL1_1_N" SITE "W3";\r
+# # LOCATE COMP "DQLL1_2_N" SITE "W1";\r
+# # LOCATE COMP "DQLL1_3_N" SITE "W9";\r
+# # LOCATE COMP "DQLL1_4_N" SITE "AA8";\r
+# # LOCATE COMP "DQLL2_0_N" SITE "AC4";\r
+# # LOCATE COMP "DQLL2_1_N" SITE "AC1";\r
+# # LOCATE COMP "DQLL2_2_N" SITE "AB3";\r
+# # LOCATE COMP "DQLL2_3_N" SITE "AB8";\r
+# # LOCATE COMP "DQLL2_4_N" SITE "AB6";\r
+# # LOCATE COMP "DQLL3_0_N" SITE "AE3";\r
+# # LOCATE COMP "DQLL3_1_N" SITE "AC10"\r
+# # LOCATE COMP "DQLL3_2_N" SITE "AE1";\r
+# # LOCATE COMP "DQLL3_3_N" SITE "AD3";\r
+# # LOCATE COMP "DQLL3_4_N" SITE "AC8";\r
+# # LOCATE COMP "DQLR0_0_N" SITE "AB33"\r
+# # LOCATE COMP "DQLR0_1_N" SITE "AA26"\r
+# # LOCATE COMP "DQLR0_2_N" SITE "AC33"\r
+# # LOCATE COMP "DQLR0_3_N" SITE "AA30"\r
+# # LOCATE COMP "DQLR0_4_N" SITE "AA27"\r
+# # LOCATE COMP "DQLR1_0_N" SITE "AD30"\r
+# # LOCATE COMP "DQLR1_1_N" SITE "AB31"\r
+# # LOCATE COMP "DQLR1_2_N" SITE "AE33"\r
+# # LOCATE COMP "DQLR1_3_N" SITE "AD34"\r
+# # LOCATE COMP "DQLR1_4_N" SITE "AG34"\r
+# # LOCATE COMP "DQLR2_0_N" SITE "W29";\r
+# # LOCATE COMP "DQLR2_1_N" SITE "W26";\r
+# # LOCATE COMP "DQLR2_2_N" SITE "W33";;\r
+# # LOCATE COMP "DQLR2_3_N" SITE "Y33";;\r
+# # LOCATE COMP "DQLR2_4_N" SITE "Y25";\r
+# # LOCATE COMP "DQSLL0_C" SITE "AB9";\r
+# # LOCATE COMP "DQSLL1_C" SITE "Y6";\r
+# # LOCATE COMP "DQSLL2_C" SITE "AE5";\r
+# # LOCATE COMP "DQSLL3_C" SITE "AK1";\r
+# # LOCATE COMP "DQSLR0_C" SITE "AC30"\r
+# # LOCATE COMP "DQSLR1_C" SITE "AB25";\r
+# # LOCATE COMP "DQSLR2_C" SITE "AA29";\r
+# # LOCATE COMP "DQSUL0_C" SITE "M9";;\r
+# # LOCATE COMP "DQSUL1_C" SITE "L9";;\r
+# # LOCATE COMP "DQSUL2_C" SITE "H3";;\r
+# # LOCATE COMP "DQSUL3_C" SITE "N10";;\r
+# # LOCATE COMP "DQSUR0_C" SITE "M27";;\r
+# # LOCATE COMP "DQSUR1_C" SITE "N28";;\r
+# # LOCATE COMP "DQSUR2_C" SITE "U30";;\r
+# # LOCATE COMP "DQUL0_0_N" SITE "L4";;\r
+# # LOCATE COMP "DQUL0_1_N" SITE "M3";;\r
+# # LOCATE COMP "DQUL0_2_N" SITE "K5";;\r
+# # LOCATE COMP "DQUL0_3_N" SITE "M1";;\r
+# # LOCATE COMP "DQUL0_4_N" SITE "L6";;\r
+# # LOCATE COMP "DQUL1_0_N" SITE "L1";;\r
+# # LOCATE COMP "DQUL1_1_N" SITE "K1";;\r
+# # LOCATE COMP "DQUL1_2_N" SITE "K3";;\r
+# # LOCATE COMP "DQUL1_3_N" SITE "L7";;\r
+# # LOCATE COMP "DQUL1_4_N" SITE "J6";;\r
+# # LOCATE COMP "DQUL2_0_N" SITE "F1";;\r
+# # LOCATE COMP "DQUL2_1_N" SITE "E3";\r
+# # LOCATE COMP "DQUL2_2_N" SITE "G1";\r
+# # LOCATE COMP "DQUL2_3_N" SITE "J1";\r
+# # LOCATE COMP "DQUL2_4_N" SITE "H2";\r
+# # LOCATE COMP "DQUL3_0_N" SITE "N3";\r
+# # LOCATE COMP "DQUL3_1_N" SITE "N1";\r
+# # LOCATE COMP "DQUL3_2_N" SITE "N5";\r
+# # LOCATE COMP "DQUL3_3_N" SITE "P4";\r
+# # LOCATE COMP "DQUL3_4_N" SITE "P8";\r
+# # LOCATE COMP "DQUR0_0_N" SITE "M25";\r
+# # LOCATE COMP "DQUR0_1_N" SITE "L31";\r
+# # LOCATE COMP "DQUR0_2_N" SITE "L33";;\r
+# # LOCATE COMP "DQUR0_3_N" SITE "K30";\r
+# # LOCATE COMP "DQUR0_4_N" SITE "K33";\r
+# # LOCATE COMP "DQUR1_0_N" SITE "N29";\r
+# # LOCATE COMP "DQUR1_1_N" SITE "P26";\r
+# # LOCATE COMP "DQUR1_2_N" SITE "N31";\r
+# # LOCATE COMP "DQUR1_3_N" SITE "N33";\r
+# # LOCATE COMP "DQUR1_4_N" SITE "P27";;\r
+# # LOCATE COMP "DQUR2_0_N" SITE "T31";;\r
+# # LOCATE COMP "DQUR2_1_N" SITE "T27";;\r
+# # LOCATE COMP "DQUR2_2_N" SITE "U31";;\r
+# # LOCATE COMP "DQUR2_3_N" SITE "T33";;\r
+# # LOCATE COMP "DQUR2_4_N" SITE "U27";\r
+# \r
+# LOCATE COMP "DQLL0_0" SITE "AA2"; #was "DQLL0_0_P" 1\r
+# LOCATE COMP "DQLL0_1" SITE "AB2"; #was "DQLL0_1_P" 5\r
+# LOCATE COMP "DQLL0_2" SITE "AA4"; #was "DQLL0_2_P" 9\r
+# LOCATE COMP "DQSLL0" SITE "AA10"; #was "DQSLL0_T" 13\r
+# LOCATE COMP "DQLL0_3" SITE "AA5"; #was "DQLL0_3_P" 17\r
+# LOCATE COMP "DQLL0_4" SITE "Y7"; #was "DQLL0_4_P" 21\r
+# LOCATE COMP "DQLL2_0" SITE "AC5"; #was "DQLL2_0_P" 25\r
+# LOCATE COMP "DQLL2_1" SITE "AC2"; #was "DQLL2_1_P" 29\r
+# LOCATE COMP "DQLL2_2" SITE "AB4"; #was "DQLL2_2_P" 33\r
+# LOCATE COMP "DQSLL2" SITE "AD5"; #was "DQSLL2_T" 37\r
+# LOCATE COMP "DQLL2_3" SITE "AA9"; #was "DQLL2_3_P" 41\r
+# LOCATE COMP "DQLL2_4" SITE "AB7"; #was "DQLL2_4_P" 45\r
+# LOCATE COMP "DQUL3_0" SITE "N4"; #was "DQUL3_0_P" 49\r
+# LOCATE COMP "DQUL3_1" SITE "N2"; #was "DQUL3_1_P" 53\r
+# LOCATE COMP "DQUL3_2" SITE "M5"; #was "DQUL3_2_P" 57\r
+# LOCATE COMP "DQSUL3" SITE "M10"; #was "DQSUL3_T" 61\r
+# LOCATE COMP "DQUL3_3" SITE "P5"; #was "DQUL3_3_P" 65\r
+# LOCATE COMP "DQUL3_4" SITE "N8"; #was "DQUL3_4_P" 69\r
+# LOCATE COMP "DQUL1_0" SITE "L2"; #was "DQUL1_0_P" 73\r
+# LOCATE COMP "DQUL1_1" SITE "K2"; #was "DQUL1_1_P" 77\r
+# LOCATE COMP "DQUL1_2" SITE "K4"; #was "DQUL1_2_P" 81\r
+# LOCATE COMP "DQSUL1" SITE "L10"; #was "DQSUL1_T" 85\r
+# LOCATE COMP "DQUL1_3" SITE "M8"; #was "DQUL1_3_P" 89\r
+# LOCATE COMP "DQUL1_4" SITE "K7"; #was "DQUL1_4_P" 93\r
+# \r
+# LOCATE COMP "DQUR0_0" SITE "L26"; #was "DQUR0_0_P" 105\r
+# LOCATE COMP "DQUR0_1" SITE "L32"; #was "DQUR0_1_P" 109\r
+# LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113\r
+# LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117\r
+# LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121\r
+# LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125\r
+# LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129\r
+# LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133\r
+# LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137\r
+# LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141\r
+# LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145\r
+# LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149\r
+# \r
+# LOCATE COMP "DQLR1_0" SITE "AD31"; #was "DQLR1_0_P" 169\r
+# LOCATE COMP "DQLR1_1" SITE "AB32"; #was "DQLR1_1_P" 173\r
+# LOCATE COMP "DQLR1_2" SITE "AE34"; #was "DQLR1_2_P" 177\r
+# LOCATE COMP "DQSLR1" SITE "AB26"; #was "DQSLR1_T" 181\r
+# LOCATE COMP "DQLR1_3" SITE "AD33"; #was "DQLR1_3_P" 185\r
+# LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189\r
+# \r
+# \r
+# LOCATE COMP "DQLL3_0" SITE "AE4"; #was "DQLL3_0_P" 2\r
+# LOCATE COMP "DQLL3_1" SITE "AB10"; #was "DQLL3_1_P" 6\r
+# LOCATE COMP "DQLL3_2" SITE "AE2"; #was "DQLL3_2_P" 10\r
+# LOCATE COMP "DQSLL3" SITE "AJ1"; #was "DQSLL3_T" 14\r
+# LOCATE COMP "DQLL3_3" SITE "AD4"; #was "DQLL3_3_P" 18\r
+# LOCATE COMP "DQLL3_4" SITE "AC9"; #was "DQLL3_4_P" 22\r
+# LOCATE COMP "DQLL1_0" SITE "Y2"; #was "DQLL1_0_P" 26\r
+# LOCATE COMP "DQLL1_1" SITE "W4"; #was "DQLL1_1_P" 30\r
+# LOCATE COMP "DQLL1_2" SITE "W2"; #was "DQLL1_2_P" 34\r
+# LOCATE COMP "DQSLL1" SITE "W6"; #was "DQSLL1_T" 38\r
+# LOCATE COMP "DQLL1_3" SITE "W8"; #was "DQLL1_3_P" 42\r
+# LOCATE COMP "DQLL1_4" SITE "Y8"; #was "DQLL1_4_P" 46\r
+# LOCATE COMP "DQUL2_0" SITE "F2"; #was "DQUL2_0_P" 50\r
+# LOCATE COMP "DQUL2_1" SITE "F3"; #was "DQUL2_1_P" 54\r
+# LOCATE COMP "DQUL2_2" SITE "G2"; #was "DQUL2_2_P" 58\r
+# LOCATE COMP "DQSUL2" SITE "G3"; #was "DQSUL2_T" 62\r
+# LOCATE COMP "DQUL2_3" SITE "H1"; #was "DQUL2_3_P" 66\r
+# LOCATE COMP "DQUL2_4" SITE "J3"; #was "DQUL2_4_P" 70\r
+# LOCATE COMP "DQUL0_0" SITE "L5"; #was "DQUL0_0_P" 74\r
+# LOCATE COMP "DQUL0_1" SITE "M4"; #was "DQUL0_1_P" 78\r
+# LOCATE COMP "DQUL0_2" SITE "K6"; #was "DQUL0_2_P" 82\r
+# LOCATE COMP "DQSUL0" SITE "N9"; #was "DQSUL0_T" 86\r
+# LOCATE COMP "DQUL0_3" SITE "M2"; #was "DQUL0_3_P" 90\r
+# LOCATE COMP "DQUL0_4" SITE "M7"; #was "DQUL0_4_P" 94\r
+# \r
+# LOCATE COMP "DQUR1_0" SITE "N30"; #was "DQUR1_0_P" 106\r
+# LOCATE COMP "DQUR1_1" SITE "N26"; #was "DQUR1_1_P" 110\r
+# LOCATE COMP "DQUR1_2" SITE "N32"; #was "DQUR1_2_P" 114\r
+# LOCATE COMP "DQSUR1" SITE "N27"; #was "DQSUR1_T" 118\r
+# LOCATE COMP "DQUR1_3" SITE "N34"; #was "DQUR1_3_P" 122\r
+# LOCATE COMP "DQUR1_4" SITE "P28"; #was "DQUR1_4_P" 126\r
+# LOCATE COMP "DQUR2_0" SITE "T32"; #was "DQUR2_0_P" 130\r
+# LOCATE COMP "DQUR2_1" SITE "T26"; #was "DQUR2_1_P" 134\r
+# LOCATE COMP "DQUR2_2" SITE "U32"; #was "DQUR2_2_P" 138\r
+# LOCATE COMP "DQSUR2" SITE "T30"; #was "DQSUR2_T" 142\r
+# LOCATE COMP "DQUR2_3" SITE "T34"; #was "DQUR2_3_P" 146\r
+# LOCATE COMP "DQUR2_4" SITE "U26"; #was "DQUR2_4_P" 150\r
+# \r
+# LOCATE COMP "DQLR2_0" SITE "W30"; #was "DQLR2_0_P" 170\r
+# LOCATE COMP "DQLR2_1" SITE "W27"; #was "DQLR2_1_P" 174\r
+# LOCATE COMP "DQLR2_2" SITE "W34"; #was "DQLR2_2_P" 178\r
+# LOCATE COMP "DQSLR2" SITE "Y30"; #was "DQSLR2_T" 182\r
+# LOCATE COMP "DQLR2_3" SITE "Y34"; #was "DQLR2_3_P" 186\r
+# LOCATE COMP "DQLR2_4" SITE "Y26"; #was "DQLR2_4_P" 190\r
+# \r
+# DEFINE PORT GROUP "DQ_group" "DQ*" ;\r
+# IOBUF GROUP "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; \r
+\r
+\r
+\r
+\r
+#################################################################\r
+# Pin-header IO\r
+#################################################################\r
+LOCATE COMP "HDR_IO_1" SITE "AP28";\r
+LOCATE COMP "HDR_IO_2" SITE "AN28";\r
+LOCATE COMP "HDR_IO_3" SITE "AP27";\r
+LOCATE COMP "HDR_IO_4" SITE "AN27";\r
+LOCATE COMP "HDR_IO_5" SITE "AM27";\r
+LOCATE COMP "HDR_IO_6" SITE "AL27";\r
+LOCATE COMP "HDR_IO_7" SITE "AH26";\r
+LOCATE COMP "HDR_IO_8" SITE "AG26";\r
+LOCATE COMP "HDR_IO_9" SITE "AM28";\r
+LOCATE COMP "HDR_IO_10" SITE "AL28";\r
+DEFINE PORT GROUP "HDR_group" "HDR*" ;\r
+IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;\r
+\r
+#################################################################\r
+# KEL Connector\r
+#################################################################\r
+# # LOCATE COMP "KEL1_N" SITE "AP6";\r
+# # LOCATE COMP "KEL2_N" SITE "AP3";\r
+# # LOCATE COMP "KEL3_N" SITE "AN2";\r
+# # LOCATE COMP "KEL4_N" SITE "AM3";\r
+# # LOCATE COMP "KEL5_N" SITE "AM5";\r
+# # LOCATE COMP "KEL6_N" SITE "AN6";\r
+# # LOCATE COMP "KEL7_N" SITE "AM4";\r
+# # LOCATE COMP "KEL8_N" SITE "AJ6";\r
+# # LOCATE COMP "KEL9_N" SITE "AJ3";\r
+# # LOCATE COMP "KEL10_N" SITE "AK3";\r
+# # LOCATE COMP "KEL11_N" SITE "AD8";\r
+# # LOCATE COMP "KEL12_N" SITE "AK4";\r
+# # LOCATE COMP "KEL13_N" SITE "V3";\r
+# # LOCATE COMP "KEL14_N" SITE "W5";\r
+# # LOCATE COMP "KEL15_N" SITE "T8";\r
+# # LOCATE COMP "KEL16_N" SITE "T1";\r
+# # LOCATE COMP "KEL17_N" SITE "P6";\r
+# # LOCATE COMP "KEL18_N" SITE "T7";\r
+# # LOCATE COMP "KEL19_N" SITE "R1";\r
+# # LOCATE COMP "KEL20_N" SITE "P10";\r
+# # LOCATE COMP "KEL21_N" SITE "AP30";\r
+# # LOCATE COMP "KEL22_N" SITE "AP32";\r
+# # LOCATE COMP "KEL23_N" SITE "AN33";\r
+# # LOCATE COMP "KEL24_N" SITE "AN31";\r
+# # LOCATE COMP "KEL25_N" SITE "AM32";\r
+# # LOCATE COMP "KEL26_N" SITE "AN29";\r
+# # LOCATE COMP "KEL27_N" SITE "AM31";\r
+# # LOCATE COMP "KEL28_N" SITE "AM30";\r
+# # LOCATE COMP "KEL29_N" SITE "AL33";\r
+# # LOCATE COMP "KEL30_N" SITE "AK31";\r
+# # LOCATE COMP "KEL31_N" SITE "AJ33";\r
+# # LOCATE COMP "KEL32_N" SITE "AK32";\r
+# # LOCATE COMP "KEL33_N" SITE "AF31";\r
+# # LOCATE COMP "KEL34_N" SITE "AE31";\r
+# # LOCATE COMP "KEL35_N" SITE "AE29";\r
+# # LOCATE COMP "KEL36_N" SITE "AD25";\r
+# # LOCATE COMP "KEL37_N" SITE "L30";\r
+# # LOCATE COMP "KEL38_N" SITE "AB27";\r
+# # LOCATE COMP "KEL39_N" SITE "M33";\r
+# # LOCATE COMP "KEL40_N" SITE "M28";\r
+LOCATE COMP "KEL_1" SITE "AP5";\r
+LOCATE COMP "KEL_2" SITE "AP2";\r
+LOCATE COMP "KEL_3" SITE "AN1";\r
+LOCATE COMP "KEL_4" SITE "AN3";\r
+LOCATE COMP "KEL_5" SITE "AL5";\r
+LOCATE COMP "KEL_6" SITE "AM6";\r
+LOCATE COMP "KEL_7" SITE "AL4";\r
+LOCATE COMP "KEL_8" SITE "AJ5";\r
+LOCATE COMP "KEL_9" SITE "AJ2";\r
+LOCATE COMP "KEL_10" SITE "AL3";\r
+LOCATE COMP "KEL_11" SITE "AD9";\r
+LOCATE COMP "KEL_12" SITE "AJ4";\r
+LOCATE COMP "KEL_13" SITE "V4";\r
+LOCATE COMP "KEL_14" SITE "V5";\r
+LOCATE COMP "KEL_15" SITE "T9";\r
+LOCATE COMP "KEL_16" SITE "T2";\r
+LOCATE COMP "KEL_17" SITE "P7";\r
+LOCATE COMP "KEL_18" SITE "R8";\r
+LOCATE COMP "KEL_19" SITE "R2";\r
+LOCATE COMP "KEL_20" SITE "P9";\r
+LOCATE COMP "KEL_21" SITE "AP29";\r
+LOCATE COMP "KEL_22" SITE "AP33";\r
+LOCATE COMP "KEL_23" SITE "AN34";\r
+LOCATE COMP "KEL_24" SITE "AP31";\r
+LOCATE COMP "KEL_25" SITE "AN32";\r
+LOCATE COMP "KEL_26" SITE "AM29";\r
+LOCATE COMP "KEL_27" SITE "AL31";\r
+LOCATE COMP "KEL_28" SITE "AL30";\r
+LOCATE COMP "KEL_29" SITE "AL34";\r
+LOCATE COMP "KEL_30" SITE "AJ31";\r
+LOCATE COMP "KEL_31" SITE "AH33";\r
+LOCATE COMP "KEL_32" SITE "AL32";\r
+LOCATE COMP "KEL_33" SITE "AF32";\r
+LOCATE COMP "KEL_34" SITE "AE32";\r
+LOCATE COMP "KEL_35" SITE "AE30";\r
+LOCATE COMP "KEL_36" SITE "AD26";\r
+LOCATE COMP "KEL_37" SITE "M29";\r
+LOCATE COMP "KEL_38" SITE "AC28";\r
+LOCATE COMP "KEL_39" SITE "M34";\r
+LOCATE COMP "KEL_40" SITE "L28";\r
+DEFINE PORT GROUP "KEL_group" "KEL*" ;\r
+IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+\r
+#################################################################\r
+# Many LED\r
+#################################################################\r
+LOCATE COMP "LED_RJ_GREEN_0" SITE "C25";\r
+LOCATE COMP "LED_RJ_RED_0" SITE "D25";\r
+LOCATE COMP "LED_GREEN" SITE "D24";\r
+LOCATE COMP "LED_ORANGE" SITE "E24";\r
+LOCATE COMP "LED_RED" SITE "K23";\r
+LOCATE COMP "LED_RJ_GREEN_1" SITE "G26";\r
+LOCATE COMP "LED_RJ_RED_1" SITE "G25";\r
+LOCATE COMP "LED_YELLOW" SITE "K24";\r
+IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ;\r
+IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ;\r
+\r
+LOCATE COMP "LED_SFP_GREEN_0" SITE "B4";\r
+LOCATE COMP "LED_SFP_GREEN_1" SITE "A6";\r
+LOCATE COMP "LED_SFP_RED_0" SITE "A3";\r
+LOCATE COMP "LED_SFP_RED_1" SITE "A8";\r
+DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ;\r
+IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ;\r
+\r
+LOCATE COMP "LED_WHITE_0" SITE "A32";\r
+LOCATE COMP "LED_WHITE_1" SITE "A33";\r
+DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ;\r
+IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ;\r
+\r
+#################################################################\r
+# SFP Control Signals\r
+#################################################################\r
+LOCATE COMP "SFP_LOS_0" SITE "B6";\r
+LOCATE COMP "SFP_LOS_1" SITE "C9";\r
+LOCATE COMP "SFP_MOD0_0" SITE "A5";\r
+LOCATE COMP "SFP_MOD0_1" SITE "K11";\r
+LOCATE COMP "SFP_MOD1_0" SITE "B7";\r
+LOCATE COMP "SFP_MOD1_1" SITE "J11";\r
+LOCATE COMP "SFP_MOD2_0" SITE "A7";\r
+LOCATE COMP "SFP_MOD2_1" SITE "D9";\r
+# LOCATE COMP "SFP_RATE_SEL_0" SITE "A4";\r
+# LOCATE COMP "SFP_RATE_SEL_1" SITE "C8";\r
+LOCATE COMP "SFP_TX_DIS_0" SITE "D6";\r
+LOCATE COMP "SFP_TX_DIS_1" SITE "A9";\r
+# LOCATE COMP "SFP_TX_FAULT_0" SITE "C5";\r
+# LOCATE COMP "SFP_TX_FAULT_1" SITE "B8";\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
+IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ;\r
+\r
+\r
+\r
+#################################################################\r
+# Serdes Output Switch\r
+#################################################################\r
+LOCATE COMP "PCSSW_ENSMB" SITE "B3";\r
+LOCATE COMP "PCSSW_EQ_0" SITE "B1";\r
+LOCATE COMP "PCSSW_EQ_1" SITE "B2";\r
+LOCATE COMP "PCSSW_EQ_2" SITE "E4";\r
+LOCATE COMP "PCSSW_EQ_3" SITE "D4";\r
+LOCATE COMP "PCSSW_PE_0" SITE "C3";\r
+LOCATE COMP "PCSSW_PE_1" SITE "C4";\r
+LOCATE COMP "PCSSW_PE_2" SITE "D3";\r
+LOCATE COMP "PCSSW_PE_3" SITE "C2";\r
+LOCATE COMP "PCSSW_1" SITE "D5";\r
+LOCATE COMP "PCSSW_0" SITE "A2";\r
+LOCATE COMP "PCSSW_2" SITE "E13";\r
+LOCATE COMP "PCSSW_3" SITE "F13";\r
+LOCATE COMP "PCSSW_4" SITE "G13";\r
+LOCATE COMP "PCSSW_5" SITE "H14";\r
+LOCATE COMP "PCSSW_6" SITE "A13";\r
+LOCATE COMP "PCSSW_7" SITE "B13";\r
+DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ;\r
+IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
+\r
+\r
+#################################################################\r
+# ADC\r
+#################################################################\r
+LOCATE COMP "ADC_CLK" SITE "A14"; \r
+LOCATE COMP "ADC_CS" SITE "B14"; \r
+LOCATE COMP "ADC_DIN" SITE "G17"; \r
+LOCATE COMP "ADC_DOUT" SITE "G16"; \r
+IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ;\r
+IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+\r
+\r
+#################################################################\r
+# RJ-45 connectors\r
+#################################################################\r
+LOCATE COMP "RJ_IO_1" SITE "R28";\r
+LOCATE COMP "RJ_IO_2" SITE "R31";\r
+LOCATE COMP "RJ_IO_3" SITE "R26";\r
+LOCATE COMP "RJ_IO_4" SITE "R34";\r
+#LOCATE COMP "RJ_IO_1_N" SITE "R27";\r
+#LOCATE COMP "RJ_IO_2_N" SITE "R30";\r
+#LOCATE COMP "RJ_IO_3_N" SITE "R25";\r
+#LOCATE COMP "RJ_IO_4_N" SITE "R33";\r
+IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ;\r
+IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25 ;\r
+IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ;\r
+IOBUF PORT "RJ_IO_4" IO_TYPE=LVDS25E ;\r
+\r
+\r
+LOCATE COMP "SPARE_IN_0" SITE "K31";\r
+LOCATE COMP "SPARE_IN_1" SITE "R4";\r
+#LOCATE COMP "SPARE_IN0_N" SITE "K32";\r
+#LOCATE COMP "SPARE_IN1_N" SITE "R3";\r
+IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+IOBUF PORT "SPARE_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
+\r
+\r
+\r
+#################################################################\r
+# Flash ROM and Reboot\r
+#################################################################\r
+LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK"\r
+LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" \r
+LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" \r
+LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT"\r
+LOCATE COMP "PROGRAMN" SITE "C31";\r
+\r
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
+IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE;\r
+IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;\r
+\r
+LOCATE COMP "ENPIRION_CLOCK" SITE "H23";\r
+IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+\r
+\r
+#################################################################\r
+# Misc\r
+#################################################################\r
+LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB\r
+IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;\r
+\r
+\r
+#################################################################\r
+# Trigger I/O\r
+#################################################################\r
+LOCATE COMP "TEST_LINE_0" SITE "A19";\r
+LOCATE COMP "TEST_LINE_1" SITE "B19";\r
+LOCATE COMP "TEST_LINE_2" SITE "K20";\r
+LOCATE COMP "TEST_LINE_3" SITE "L19";\r
+LOCATE COMP "TEST_LINE_4" SITE "C19";\r
+LOCATE COMP "TEST_LINE_5" SITE "D19";\r
+LOCATE COMP "TEST_LINE_6" SITE "J19";\r
+LOCATE COMP "TEST_LINE_7" SITE "K19";\r
+LOCATE COMP "TEST_LINE_8" SITE "A20";\r
+LOCATE COMP "TEST_LINE_9" SITE "B20";\r
+LOCATE COMP "TEST_LINE_10" SITE "G20";\r
+LOCATE COMP "TEST_LINE_11" SITE "G21";\r
+LOCATE COMP "TEST_LINE_12" SITE "C20";\r
+LOCATE COMP "TEST_LINE_13" SITE "D20";\r
+LOCATE COMP "TEST_LINE_14" SITE "F21";\r
+LOCATE COMP "TEST_LINE_15" SITE "F22";\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
\ No newline at end of file
system("cat $TOPNAME.lpf >> $WORKDIR/$TOPNAME.lpf");
if($include_TDC) {
- system("cat ../tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
- system("cat ../tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf");
- system("cat ../tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+ system("cat ../../trb3sc/tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+ system("cat ../../trb3sc/tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf");
+ system("cat ../../trb3sc/tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
}
if($include_GBE) {
--- /dev/null
+../scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--TDC settings
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
+ --ring buffer size: 32,64,96,128,dyn
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F3CF";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62";
+
+
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_YES;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(0,8)); --table version 20
+ t(7 downto 0) := (others => '0'); --std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
+ t(11 downto 8) := (others => '0'); --std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
+ t(14 downto 14) := "0"; --std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
+ t(15 downto 15) := "0"; --std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
+ t(23 downto 16) := (others => '0'); --std_logic_vector(to_unsigned(ADC_CHANNELS,8));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+TOPNAME => "trb3sc_tdctemplate",
+lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/d/jspc29/lattice/diamond/3.5_x64',
+synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
+synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 1,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+
--- /dev/null
+TOPNAME => "trb3sc_tdctemplate",
+lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.4_x64/',
+synplify_path => '/opt/synplicity/J-2014.09-SP2',
+#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+synplify_command => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp",
+
+nodelist_file => 'nodelist_gsi_template.txt',
+
+include_TDC => 1,
+
+firefox_open => 0,
+
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 24
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
--- /dev/null
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /d/jspc22/trb/git/trb3sc/template/synplify.fdc
+# Written on Thu Jun 18 11:51:05 2015
+# by Synplify Pro, I-2014.03L-SP1 FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+create_clock -name {clk240} {p:CLK_CORE_PCLK} -period {4.16}
+create_clock -name {clksys} {n:THE_CLOCK_RESET.SYS_CLK_OUT} -period {10}
+create_clock -name {clktxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.tx_full_clk_ch3} -period {5}
+create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs3\.THE_SERDES.rx_full_clk_ch3} -period {5}
+create_clock -name {clkintfull} {n:THE_CLOCK_RESET.gen_norecov_clock\.gen_200\.THE_INT_PLL.CLKOP} -period {5}
+
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+###==== END "Compile Points"
+
+
+
+
+
+
+
+
+
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3sc_tdctemplate"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3sc_tdctemplate.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+#TDC
+add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+
+
+add_file -vhdl -lib work "./trb3sc_tdctemplate.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.tdc_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define.all;
+
+entity trb3sc_tdctemplate is
+ port(
+ CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
+ CLK_CORE_PCLK : in std_logic; --Main Oscillator
+ CLK_EXT_PLL_LEFT : in std_logic; --External Clock
+ --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
+ --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
+ --CLK_CORE_PLL_LEFT : in std_logic; --not used
+ --CLK_CORE_PLL_RIGHT : in std_logic; --not used
+ --CLK_EXT_PCLK : in std_logic; --not used
+ --CLK_EXT_PLL_RIGHT : in std_logic; --not used
+
+ TRIG_LEFT : in std_logic; --Trigger Input
+ --TRIG_PLL : in std_logic; --not used
+ --TRIG_RIGHT : in std_logic; --not used
+
+ --Backplane, all lines
+ BACK_GPIO : inout std_logic_vector(15 downto 0);
+ BACK_LVDS : inout std_logic_vector(1 downto 0);
+ BACK_3V3 : inout std_logic_vector(3 downto 0);
+ --Backplane for slaves on trbv3scbp1
+-- BACK_GPIO : inout std_logic_vector(3 downto 0);
+
+ --AddOn Connector
+ --to be added
+
+ --KEL Connector
+ KEL : in std_logic_vector(40 downto 1);
+
+ --Additional IO
+ HDR_IO : inout std_logic_vector(10 downto 1);
+ RJ_IO : inout std_logic_vector(3 downto 0);
+ SPARE_IN : in std_logic_vector(1 downto 0);
+
+ --LED
+ LED_GREEN : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);
+ LED_RJ_RED : out std_logic_vector(1 downto 0);
+ LED_WHITE : out std_logic_vector(1 downto 0);
+ LED_SFP_GREEN : out std_logic_vector(1 downto 0);
+ LED_SFP_RED : out std_logic_vector(1 downto 0);
+
+ --SFP
+ SFP_LOS : in std_logic_vector(1 downto 0);
+ SFP_MOD0 : in std_logic_vector(1 downto 0);
+ SFP_MOD1 : inout std_logic_vector(1 downto 0) := (others => 'Z');
+ SFP_MOD2 : inout std_logic_vector(1 downto 0) := (others => 'Z');
+ SFP_TX_DIS : out std_logic_vector(1 downto 0) := (others => '0');
+
+ SERDES_TX : out std_logic_vector(1 downto 0);
+ SERDES_RX : in std_logic_vector(1 downto 0);
+
+ --Serdes switch
+ PCSSW_ENSMB : out std_logic;
+ PCSSW_EQ : out std_logic_vector(3 downto 0);
+ PCSSW_PE : out std_logic_vector(3 downto 0);
+ PCSSW : out std_logic_vector(7 downto 0);
+
+ --ADC
+ ADC_CLK : out std_logic;
+ ADC_CS : out std_logic;
+ ADC_DIN : out std_logic;
+ ADC_DOUT : in std_logic;
+
+ --Flash, 1-wire, Reload
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_IN : out std_logic;
+ FLASH_OUT : in std_logic;
+ PROGRAMN : out std_logic;
+ ENPIRION_CLOCK : out std_logic;
+ TEMPSENS : inout std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_IN : signal is true;
+ attribute syn_useioff of FLASH_OUT : signal is true;
+
+
+ --Serdes: Backplane
+ --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane
+ --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,--
+ --SFP D0,B3(D1) D0: GbE, B3: TrbNet
+
+
+end entity;
+
+architecture trb3sc_arch of trb3sc_tdctemplate is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ signal time_counter : unsigned(31 downto 0) := (others => '0');
+ signal led : std_logic_vector(1 downto 0);
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+
+ --READOUT
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 0);
+
+ signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx : CTRLBUS_TX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal clock_select : std_logic;
+
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+
+ --TDC
+ signal hit_in_i : std_logic_vector(64 downto 1);
+ signal logic_analyser_i : std_logic_vector(15 downto 0);
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_keep of bussci_rx : signal is true;
+ attribute syn_preserve of bussci_rx : signal is true;
+ attribute syn_keep of bustools_rx : signal is true;
+ attribute syn_preserve of bustools_rx : signal is true;
+ attribute syn_keep of bustc_rx : signal is true;
+ attribute syn_preserve of bustc_rx : signal is true;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => med2int(0).clk_full,
+ NET_CLK_HALF_IN => med2int(0).clk_half,
+ RESET_FROM_NET => med2int(0).stat_op(13),
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
+ );
+
+ pll_calibration : entity work.pll_in125_out33
+ port map (
+ CLK => CLK_SUPPL_PCLK,
+ CLKOP => clk_cal,
+ LOCK => open);
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+
+ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+ generic map(
+ SERDES_NUM => 3,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_RX(0),
+ SD_RXD_N_IN => SERDES_RX(1),
+ SD_TXD_P_OUT => SERDES_TX(0),
+ SD_TXD_N_OUT => SERDES_TX(1),
+ SD_REFCLK_P_IN => '0',
+ SD_REFCLK_N_IN => '0',
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TX_DIS(1),
+ --Control Interface
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+ SFP_TX_DIS(0) <= '1';
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
+ generic map (
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 10,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**8,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**8
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
+
+ --Slow Control Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ ONEWIRE_INOUT => TEMPSENS,
+ --Timing registers
+ TIMERS_OUT => timer
+ );
+
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => bustdc_rx, --TDC config
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => bustdc_tx,
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ --Header
+ HEADER_IO => HDR_IO,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ --ADC
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Switches
+---------------------------------------------------------------------------
+--Serdes Select
+ PCSSW_ENSMB <= '0';
+ PCSSW_EQ <= x"0";
+ PCSSW_PE <= x"F";
+ PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+
+ RJ_IO <= "0000";
+
+ BACK_GPIO <= (others => 'Z');
+ BACK_LVDS <= (others => '0');
+ BACK_3V3 <= (others => 'Z');
+
+
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------
+ lcd_data(15 downto 0) <= timer.network_address;
+ lcd_data(47 downto 16) <= timer.microsecond;
+ lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32));
+ lcd_data(511 downto 80) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+ LED_GREEN <= debug_clock_reset(0);
+ LED_ORANGE <= debug_clock_reset(1);
+ LED_RED <= not sed_error_i;
+ LED_YELLOW <= debug_clock_reset(2);
+ LED_WHITE(0) <= time_counter(26) and time_counter(19);
+ LED_WHITE(1) <= time_counter(20);
+ LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_sys);
+ time_counter <= time_counter + 1;
+ if reset_i = '1' then
+ time_counter <= (others => '0');
+ end if;
+ end process;
+
+
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : TDC_record
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => clk_full_osc,
+ CLK_READOUT => clk_sys, -- Clock for the readout
+ REFERENCE_TIME => TRIG_LEFT, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+ -- Trigger signals from handler
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx(0),
+ --
+ LOGIC_ANALYSER_OUT => logic_analyser_i,
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx
+ );
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i(40 downto 1) <= KEL(40 downto 1);
+ end generate;
+
+ -- For ToT Measurements
+ gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+ Gen_Hit_In_Signals : for i in 1 to 20 generate
+ hit_in_i(i*2-1) <= KEL(i);
+ hit_in_i(i*2) <= not KEL(i);
+ end generate Gen_Hit_In_Signals;
+ end generate;
+
+
+
+end architecture;
+
+
+
jspc29 / trb3sc.git / commitdiff