flexible clock speed for UART interface

diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd
index d4ef19b48fa73f0ebcf5d69d0f599d6105592712..48eb2c5a311ce2764dbbf91074a06d7680b29e36 100644 (file)
--- a/source/uart_sctrl.vhd
+++ b/source/uart_sctrl.vhd
@@ -11,6 +11,9 @@ use machxo2.all;
 
 
 entity uart_sctrl is
+  generic(
+    CLOCK_SPEED : integer := 133000000
+    );
   port(
     CLK     : in  std_logic;
     RESET   : in  std_logic;
@@ -31,7 +34,7 @@ end entity;
 
 architecture uart_sctrl_arch of uart_sctrl is
 
-constant CLK_DIV : integer := 133000000/115200;
+constant CLK_DIV : integer := CLOCK_SPEED/115200;
 
 signal rx_data   : std_logic_vector(7 downto 0);
 signal tx_data   : std_logic_vector(7 downto 0);