\end{lstlisting}
+\subsection{Modifiers}
+
+\subsubsection*{Common Settings}
+\begin{description}
+ \item[\textsc{Configonly}] Run only configuration process, do not load FPGA designs
+ \item[\textsc{Noreset}] Don't execute a network reset
+\end{description}
+
+
+\subsubsection*{Exclude Systems}
+\begin{description}
+ \item[Nocts, Nohub, Nomdc, Norich, Norpc, \\Noshower, Nowall, Nostart, Notof] These commands remove the given system from loading settings, loading FPGA designs and the TRB list.
+ \item[\textsc{All, Tof, Rich, Rpc, Shower, Mdc, Wall, Mdc12, Mdc34}] These commands include the given systems in the network by switching on the corresponding port on the central Hub. Please note that the default (without these commands) is all detectors off!
+\end{description}
+
+
+\subsubsection*{Fixed trigger types}
+\begin{description}
+ \item[\textsc{Trgtypeshwcalib}] Force Shower Calibration trigger type 0xA
+ \item[\textsc{Trgtypeshwpedestal}] Force Shower Pedestal trigger type 0xB
+ \item[\textsc{Trgtypemdccalib}] Force MDC Calibration trigger
+ \item[\textsc{Trgtypenormal}] Force normal trigger type
+\end{description}
+
+
+\subsubsection*{CTS Settings}
+\begin{description}
+ \item[\textsc{Ctsreadoutoff}] Switch off readout on the CTS
+ \item[\textsc{Eb*}] Different Eventbuilder combinations. Available: EB0, EB1, EB2, EB3, EB01, EB0123, EB13.
+
+\end{description}
+
+\subsubsection*{RICH Settings}
+\begin{description}
+ \item[\textsc{Richnoinit}] Skip initializing ADCM and loading pedestals
+ \item[\textsc{Richdebugmode}] Switch on debug words in RICH
+ \item[\textsc{Richfullmode}] Set trigger type to RICH full data mode. Without this option, standard is normal mode.
+\end{description}
+
+
+\subsubsection*{MDC settings}
+\begin{description}
+ \item[\textsc{reg0}] Load settings for TDC register 0, overwrite default values in OEP
+ \item[\textsc{reg1}] Load settings for TDC register 1, overwrite default values in OEP
+ \item[\textsc{thresh*}] Load special threshold values for all boards. Values are given in hex: thresh10, thresh20, thresh30, thresh40, thresh50, thresh60, thresh70, thresh80, thresh90, thresha0, threshf0.
+ \item[\textsc{calib}] Temporary: run calibration triggers
+ \item[\textsc{nocms}] Temporary: use internal cms, not external signal
+\end{description}
+
+
+
--- /dev/null
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Event Builders}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Port Numbers}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The first EB on each server uses port numbers starting with 50000 (0xc350), the second process uses ports 52000 (0xcb20) and above, while the third EB uses ports 54000 (0xd2f0) and above. Sender port and receiver port are always equal. The sender MAC is of the form 02:30:DE:AD:nn:nn where nn:nn is the same as the network address and the SubEventId of the corresponding sender.
+
+The source IP is in the 192.168.100.0/24 Subnet. The lowest byte starts with 128 and the has the same offsets as the port numbers.
+
+
+\begin{table}
+\begin{center}
+\begin{tabular}{|c|c|c|c|c|c|}
+\hline
+\textbf{System} & \textbf{SubEvtId} & \textbf{EB 0 -- 3, 15} & \textbf{EB 4 -- 7} & \textbf{EB 8 -- 11} & \textbf{IP} \\
+\hline
+\hline
+Central & 0x8000 & 50000 & 52000 & 54000 & 128 \\
+MDC1/2 & 0x8100 & 50001 & 52001 & 54001 & 129 \\
+MDC3/4 & 0x8110 & 50002 & 52002 & 54002 & 130 \\
+RICH 1/2 & 0x8300 & 50003 & 52003 & 54003 & 131 \\
+RICH 3/4 & 0x8310 & 50004 & 52004 & 54004 & 132 \\
+RICH 5/6 & 0x8320 & 50005 & 52005 & 54005 & 133 \\
+RPC 1/2/3& 0x8400 & 50006 & 52006 & 54006 & 134 \\
+RPC 4/5/6& 0x8410 & 50007 & 52007 & 54007 & 135 \\
+Shower & 0x8500 & 50008 & 52008 & 54008 & 136 \\
+TOF & 0x8600 & 50009 & 52009 & 54009 & 137 \\
+FW & 0x8700 & 50010 & 52010 & 54010 & 138 \\
+Start/Veto/CTS & 0x8800 & 50011 & 52011 & 54011 & 139 \\
+\hline
+MDC1/2 1 & 0x1000 & 50016 & 52016 & 54016 & 144 \\
+MDC1/2 2 & 0x1010 & 50017 & 52017 & 54017 & 145 \\
+MDC1/2 3 & 0x1020 & 50018 & 52018 & 54018 & 146 \\
+MDC1/2 4 & 0x1030 & 50019 & 52019 & 54019 & 147 \\
+MDC1/2 5 & 0x1040 & 50020 & 52020 & 54020 & 148 \\
+MDC1/2 6 & 0x1050 & 50021 & 52021 & 54021 & 149 \\
+\hline
+MDC3/4 1 & 0x1100 & 50022 & 52016 & 54016 & 150 \\
+MDC3/4 2 & 0x1110 & 50023 & 52017 & 54017 & 151 \\
+MDC3/4 3 & 0x1120 & 50024 & 52018 & 54018 & 152 \\
+MDC3/4 4 & 0x1130 & 50025 & 52019 & 54019 & 153 \\
+MDC3/4 5 & 0x1140 & 50026 & 52020 & 54020 & 154 \\
+MDC3/4 6 & 0x1150 & 50027 & 52021 & 54021 & 155 \\
+\hline
+Shower 1 & 0x3200 & 50032 & 52032 & 54032 & 160 \\
+Shower 2 & 0x3210 & 50033 & 52033 & 54033 & 161 \\
+Shower 3 & 0x3220 & 50034 & 52034 & 54034 & 162 \\
+Shower 4 & 0x3230 & 50035 & 52035 & 54035 & 163 \\
+Shower 5 & 0x3240 & 50036 & 52036 & 54036 & 164 \\
+Shower 6 & 0x3250 & 50037 & 52037 & 54037 & 165 \\
+\hline
+\end{tabular}
+\caption{The UDP ports used to send data to the Eventbuilders}
+\label{centralhubports}
+\end{center}
+\end{table}
\ No newline at end of file
\subsection{MDC Hub}
The MDC Hub has 5 FPGAs: FPGA 1 serves the first 8 FOT, FPGA 2 the second 8 FOT, FPGA 3 controls FOT 17 to 24, FPGA 4 FOT 25 to 32. The fifth FPGA controls the Uplink (logical port 0) and connects to the other 4 FPGAs (FPGA1: port 1 -- FPGA4: port 4).
-Each MDC Hub is used to read out one sector of inner or outer MDC, two chambers on one board. FOT 1 to 16 connects the inner of the two chambers (planes 1 or 3), FOT 17 to 32 connect the outer chamber (plane 2 or 4).
-
-The OEPs on each sector are mounted in the same order as their numbers on the chamber, e.g. OEP 0 connects to FOT 0 (respectively FOT 17), OEP 8 connects to FOT 8 (24 resp.) and OEP 0xF connects to FOT 16 (or 32).
+Due to very different cable length, there is no clear rule where which OEP is connected. See section \ref{mdcaddonconnections} for details.
\section{Network Addresses}
\input{networkaddresses}
+\clearpage
+\section{Event Builder Setup}
+ \input{ebsetup}
+
\clearpage
\part{Endpoints}
\item[0x9008: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
\end{description}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{MDC AddOn Connections}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\label{mdcaddonconnections}
+Since the length of optical cables is far from optimal, the ports to which they are connected are also quite sub-optimal. Table \ref{MDCPortMap} shows what is connected where. This table is meant for DAQ operators, thus numbering starts with 0.
+
+\begin{sidewaystable}
+\begin{center}
+\begin{tabular}{|c|c|c|c|c|c|c|c|c|}
+\hline
+\textbf{Address} & \multicolumn{2}{c|}{\textbf{FPGA 1}} & \multicolumn{2}{c|}{\textbf{FPGA 2}} & \multicolumn{2}{c|}{\textbf{FPGA 3}} & \multicolumn{2}{c|}{\textbf{FPGA 4}} \\
+ & \textbf{Port 1--6} & \textbf{Port 7--8}& \textbf{Port 1--6} & \textbf{Port 7--8}& \textbf{Port 1--6} & \textbf{Port 7--8}& \textbf{Port 1--6} & \textbf{Port 7--8} \\
+ & \textbf{FOT 1--6} & \textbf{FOT 7--8}& \textbf{FOT 9--14} & \textbf{FOT 15--16}& \textbf{FOT 17--22} & \textbf{FOT 23--24}& \textbf{FOT 25--30} & \textbf{FOT 31--32} \\
+\hline
+\hline
+1000 & \multicolumn{3}{c|}{P0 S4 0-D} & -- & \multicolumn{4}{c|}{P1 S2 0-F} \\
+1010 & P1 S0 0-5 & \multicolumn{3}{c|}{P1 S5 6-F} & P1 S1 0-5 & \multicolumn{3}{c|}{P1 S0 6-F} \\
+1020 & \multicolumn{3}{c|}{P0 S0 0-D} & -- & \multicolumn{3}{c|}{P0 S5 0-D} & -- \\
+1030 & \multicolumn{3}{c|}{P0 S1 0-D} & -- & \multicolumn{3}{c|}{P0 S2 0-D} & -- \\
+1040 & \multicolumn{3}{c|}{P0 S3 0-D} & -- & \multicolumn{4}{c|}{P1 S3 0-F} \\
+1050 & \multicolumn{4}{c|}{P1 S4 0-F} & P1 S5 0-5 & \multicolumn{3}{c|}{P1 S1 6-F} \\
+1100 & \multicolumn{4}{c|}{P2 S0 0-F} & \multicolumn{4}{c|}{P3 S0 0-F} \\
+1110 & \multicolumn{4}{c|}{P3 S1 F-0} & \multicolumn{4}{c|}{P2 S1 F-0} \\
+1120 & \multicolumn{4}{c|}{P3 S2 F-0} & \multicolumn{4}{c|}{P2 S2 F-0} \\
+1130 & \multicolumn{4}{c|}{P3 S3 F-0} & \multicolumn{4}{c|}{P2 S3 F-0} \\
+1140 & \multicolumn{4}{c|}{P2 S4 0-F} & \multicolumn{4}{c|}{P3 S4 0-F} \\
+1150 & \multicolumn{4}{c|}{P2 S5 0-F} & \multicolumn{4}{c|}{P3 S5 0-F} \\
+\hline
+\end{tabular}
+\caption{Connected OEPs on each MDC AddOn FPGA. Plane (P) and Sector (S) numbers are counted starting at 0. Port numbers refer to the bit numbers inside the Hub status and control registers. Port 0 is always the uplink. To get the real network address of the hub FPGAs, the FPGA number (1--4) has to be added to the address in the left column.}
+\label{MDCPortMap}
+\end{center}
+\end{sidewaystable}
\begin{center}
\begin{tabularx}{\textwidth}{l|l|X}
\textbf{Address(es)} & \textbf{Board(s)} & \textbf{Description} \\
-0001 & CTS & \\
-0002 & Slow Control & \\
-0003 & 2nd Slow Control & if needed for monitoring \\
-0004 - 00FF & Other CTS-like boards \\
+0000 - 00FF & CTS & \\
+0100 - 01FF & Slow Control & \\
+0200 - 02FF & Other CTS-like boards \\
1000 - 17FF & MDC Concentrator & 2nd digit: inner(0) / outer(1) MDC; 3rd digit: sector (0-5), 4th digit FPGA (0-4) \\
2000 - 2FFF & MDC OEP & 2nd digit: MDC layer (0-3); 3rd digit: sector (0-5); 4th digit MBO (0-F) \\
3000 - 31FF & RICH ADCM & 3rd digit: sector (0-5); 4th digit: segment (0-4) \\
\begin{center}
\begin{tabularx}{\textwidth}{l|l|l|X}
\textbf{System} & \textbf{ID} & \textbf{Number} & \textbf{Description} \\
-CTS & 0000 - 00FF & 1 & \\
+CTS & 0000 - 00FF & 1 & only with the old CTS board!\\
MDC & 1000 - 17FF & 12 & second digit is inner(0) or outer(1) MDC, 3rd digit is the sector \\
Shower & 3200 - 33FF & 6 & 3rd digit is the sector \\
Forw. Wall & 4400 - 47FF & 3 & last digit is the segment of FW \\
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