FREQUENCY PORT CLK 30 MHz;
FREQUENCY NET CLK_100 120 MHz;
FREQUENCY NET THE_MED_INTERFACE/ff_txfullclk 30 MHz;
+ FREQUENCY NET THE_MED_INTERFACE_ff_txfullclk 30 MHz;
+ FREQUENCY NET THE_MED_INTERFACE/ff_rxfullclk 30 MHz;
FREQUENCY NET THE_MED_INTERFACE_ff_rxfullclk 30 MHz;
BLOCK NET "reset" ;
#add_file options
add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
LED_ERROR_OUT => D(2),
LED_GOOD_OUT => D(1)
);
+
+
+
---------------------------------------------------------------------
-- FEE Readout
---------------------------------------------------------------------