RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
--Internal Connection TX
- MEDIA_MED2INT : out med2int_array_t(0 to 3);
- MEDIA_INT2MED : in int2med_array_t(0 to 3);
+ MEDIA_MED2INT : out med2int_array_t(0 to 2);
+ MEDIA_INT2MED : in int2med_array_t(0 to 2);
--Sync operation
- RX_DLM : out std_logic_vector(3 downto 0) := x"0";
- RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0');
- TX_DLM : in std_logic_vector(3 downto 0) := x"0";
- TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0');
+-- RX_DLM : out std_logic_vector(3 downto 0) := x"0";
+-- RX_DLM_WORD : out std_logic_vector(31 downto 0) := (others => '0');
+-- TX_DLM : in std_logic_vector(3 downto 0) := x"0";
+-- TX_DLM_WORD : in std_logic_vector(31 downto 0) := (others => '0');
--SFP Connection
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0) := x"0"; -- SFP disable
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0) := x"0" -- SFP disable
--Control Interface
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX;
+-- BUS_RX : in CTRLBUS_RX;
+-- BUS_TX : out CTRLBUS_TX;
-- Status and control port
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+-- STAT_DEBUG : out std_logic_vector (63 downto 0);
+-- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
end entity;
architecture arch of med_ecp5_sfp_sync_4 is
+
-- Placer Directives
attribute HGROUP : string;
-- for whole architecture
signal clk_tx_full : std_logic_vector(3 downto 0);
signal reset_n : std_logic;
-signal tx_data : std_logic_vector(31 downto 0);
+signal tx_data : std_logic_vector_array_8(0 to 3);
signal tx_k : std_logic_vector(3 downto 0);
-signal rx_data : std_logic_vector(31 downto 0);
+signal rx_data : std_logic_vector_array_8(0 to 3);
signal rx_k : std_logic_vector(3 downto 0);
signal rx_error : std_logic_vector(3 downto 0);
reset_n <= not RESET;
clk_200_ref <= CLK_REF_FULL;
-SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready
+SD_TXDIS_OUT <= not rx_ready; -- when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready
-- SD_TXDIS_OUT <= RESET;
-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
-------------------------------------------------
-- Serdes
-------------------------------------------------
- THE_SERDES : entity work.pcs
- port map(
- serdes_sync_0_hdinp => hdinp,
- serdes_sync_0_hdinn => hdinn,
- serdes_sync_0_hdoutp => hdoutp,
- serdes_sync_0_hdoutn => hdoutn,
- serdes_sync_0_rxrefclk => CLK_INTERNAL_FULL,
- serdes_sync_0_rx_pclk => clk_rx_full,
- serdes_sync_0_tx_pclk => clk_tx_full,
-
- serdes_sync_0_txdata => tx_data,
- serdes_sync_0_tx_k(0) => tx_k,
- serdes_sync_0_tx_force_disp(0) => '0',
- serdes_sync_0_tx_disp_sel(0) => '0',
- serdes_sync_0_rxdata => rx_data,
- serdes_sync_0_rx_k(0) => rx_k,
- serdes_sync_0_rx_disp_err(0) => open,
- serdes_sync_0_rx_cv_err(0) => rx_error,
-
- serdes_sync_0_tx_idle_c => '0',
- serdes_sync_0_signal_detect_c => '0', --?force enable
- serdes_sync_0_rx_los_low_s => rx_los_low,
- serdes_sync_0_lsm_status_s => lsm_status,
- serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol,
- serdes_sync_0_rx_pcs_rst_c => rx_pcs_rst,
- serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst,
- serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst,
-
-
- serdes_sync_0_sci_wrdata => sci_data_in_i,
- serdes_sync_0_sci_rddata => sci_data_out_i,
- serdes_sync_0_sci_addr => sci_addr_i,
- serdes_sync_0_sci_en_dual => reset_n, --sci_ch_i(4), --?
- serdes_sync_0_sci_sel_dual => sci_ch_i(4),
- serdes_sync_0_sci_en => reset_n, --sci_ch_i(0), --?
- serdes_sync_0_sci_sel => sci_ch_i(0),
- serdes_sync_0_sci_rd => sci_read_i,
- serdes_sync_0_sci_wrn => sci_write_i,
- serdes_sync_0_sci_int => open,
-
- serdes_sync_0_cyawstn => '0', --?
- serdes_sync_0_rst_dual_c => rst_qd,
- serdes_sync_0_serdes_rst_dual_c => '0',
- serdes_sync_0_tx_pwrup_c => '1',
- serdes_sync_0_rx_pwrup_c => '1',
- serdes_sync_0_serdes_pdb => '1',
- serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst,
-
- serdes_sync_0_pll_refclki => CLK_REF_FULL,
--- sli_rst => '0',
- serdes_sync_0_pll_lol => tx_pll_lol,
- serdes_sync_0_rsl_disable => '1',
- serdes_sync_0_rsl_rst => '0', --CLEAR,
- serdes_sync_0_rsl_rx_rdy => rx_ready,
- serdes_sync_0_rsl_tx_rdy => tx_ready
- );
-
-
-gen_channels : for i in 0 to 3 generate
- tx_serdes_rst(i) <= '0'; --SD_LOS_IN; --no function
- serdes_rst_qd(i) <= '0'; --included in rst_qd
+THE_SERDES : entity work.oepserdes
+ port map (
+
+ pcs_hdinn => hdinn(0),
+ pcs_hdinp => hdinp(0),
+ pcs_hdoutn => hdoutn(0),
+ pcs_hdoutp => hdoutp(0),
+ pcs_lsm_status_s => lsm_status(0),
+ pcs_rsl_disable => '1',
+ pcs_rsl_rst => '0',
+ pcs_rsl_rx_rdy => rx_ready(0),
+ pcs_rsl_tx_rdy => tx_ready(0),
+ pcs_rst_dual_c => rst_qd(0), --ON EVERY CHANNEL?
+ pcs_rx_cdr_lol_s => rx_cdr_lol(0),
+ pcs_rx_cv_err(0) => rx_error(0),
+ pcs_rxdata => rx_data(0),
+ pcs_rx_disp_err => open,
+ pcs_rx_k(0) => rx_k(0),
+ pcs_rx_los_low_s => rx_los_low(0),
+ pcs_rx_pclk => clk_rx_full(0),
+ pcs_rx_pcs_rst_c => rx_pcs_rst(0),
+ pcs_rx_pwrup_c => '1',
+ pcs_rxrefclk => CLK_INTERNAL_FULL,
+ pcs_rx_serdes_rst_c => rx_serdes_rst(0),
+ pcs_serdes_rst_dual_c => '0',
+ pcs_signal_detect_c => '0',
+ pcs_txdata => tx_data(0),
+ pcs_tx_disp_sel(0) => '0',
+ pcs_tx_force_disp(0) => '0',
+ pcs_tx_idle_c => '0',
+ pcs_tx_k(0) => tx_k(0),
+ pcs_tx_pclk => clk_tx_full(0),
+ pcs_tx_pcs_rst_c => tx_pcs_rst(0),
+ pcs_tx_pwrup_c => '1',
+ pcs_tx_serdes_rst_c => '0',
+
+ pcs1_hdinn => hdinn(1),
+ pcs1_hdinp => hdinp(1),
+ pcs1_hdoutn => hdoutn(1),
+ pcs1_hdoutp => hdoutp(1),
+ pcs1_lsm_status_s => lsm_status(1),
+ pcs1_rsl_disable => '1',
+ pcs1_rsl_rst => '0',
+ pcs1_rsl_rx_rdy => rx_ready(1),
+ pcs1_rsl_tx_rdy => tx_ready(1),
+ pcs1_rst_dual_c => rst_qd(1),
+ pcs1_rx_cdr_lol_s => rx_cdr_lol(1),
+ pcs1_rx_cv_err(0) => rx_error(1),
+ pcs1_rxdata => rx_data(1),
+ pcs1_rx_disp_err => open,
+ pcs1_rx_k(0) => rx_k(1),
+ pcs1_rx_los_low_s => rx_los_low(1),
+ pcs1_rx_pclk => clk_rx_full(1),
+ pcs1_rx_pcs_rst_c => rx_pcs_rst(1),
+ pcs1_rx_pwrup_c => '1',
+ pcs1_rxrefclk => CLK_INTERNAL_FULL,
+ pcs1_rx_serdes_rst_c => rx_serdes_rst(1),
+ pcs1_serdes_rst_dual_c => '0',
+ pcs1_signal_detect_c => '0',
+ pcs1_txdata => tx_data(1),
+ pcs1_tx_disp_sel(0) => '0',
+ pcs1_tx_force_disp(0) => '0',
+ pcs1_tx_idle_c => '0',
+ pcs1_tx_k(0) => tx_k(1),
+ pcs1_tx_pclk => clk_tx_full(1),
+ pcs1_tx_pcs_rst_c => tx_pcs_rst(1),
+ pcs1_tx_pwrup_c => '1',
+ pcs1_tx_serdes_rst_c => '0',
+
+ pcs2_hdinn => hdinn(2),
+ pcs2_hdinp => hdinp(2),
+ pcs2_hdoutn => hdoutn(2),
+ pcs2_hdoutp => hdoutp(2),
+ pcs2_lsm_status_s => lsm_status(2),
+ pcs2_rsl_disable => '1',
+ pcs2_rsl_rst => '0',
+ pcs2_rsl_rx_rdy => rx_ready(2),
+ pcs2_rsl_tx_rdy => tx_ready(2),
+ pcs2_rst_dual_c => rst_qd(2),
+ pcs2_rx_cdr_lol_s => rx_cdr_lol(2),
+ pcs2_rx_cv_err(0) => rx_error(2),
+ pcs2_rxdata => rx_data(2),
+ pcs2_rx_disp_err => open,
+ pcs2_rx_k(0) => rx_k(2),
+ pcs2_rx_los_low_s => rx_los_low(2),
+ pcs2_rx_pclk => clk_rx_full(2),
+ pcs2_rx_pcs_rst_c => rx_pcs_rst(2),
+ pcs2_rx_pwrup_c => '1',
+ --pcs2_rxrefclk => CLK_INTERNAL_FULL, --DOES NOT EXIST !?
+ pcs2_rx_serdes_rst_c => rx_serdes_rst(2),
+ pcs2_serdes_rst_dual_c => '0',
+ pcs2_signal_detect_c => '0',
+ pcs2_txdata => tx_data(2),
+ pcs2_tx_disp_sel(0) => '0',
+ pcs2_tx_force_disp(0) => '0',
+ pcs2_tx_idle_c => '0',
+ pcs2_tx_k(0) => tx_k(2),
+ pcs2_tx_pclk => clk_tx_full(2),
+ pcs2_tx_pcs_rst_c => tx_pcs_rst(2),
+ pcs2_tx_pwrup_c => '1',
+ pcs2_tx_serdes_rst_c => '0',
+
+ pcs3_hdinn => hdinn(3),
+ pcs3_hdinp => hdinp(3),
+ pcs3_hdoutn => hdoutn(3),
+ pcs3_hdoutp => hdoutp(3),
+ pcs3_lsm_status_s => lsm_status(3),
+ pcs3_rsl_disable => '1',
+ pcs3_rsl_rst => '0',
+ pcs3_rsl_rx_rdy => rx_ready(3),
+ pcs3_rsl_tx_rdy => tx_ready(3),
+ pcs3_rst_dual_c => rst_qd(3),
+ pcs3_rx_cdr_lol_s => rx_cdr_lol(3),
+ pcs3_rx_cv_err(0) => rx_error(3),
+ pcs3_rxdata => rx_data(3),
+ pcs3_rx_disp_err => open,
+ pcs3_rx_k(0) => rx_k(3),
+ pcs3_rx_los_low_s => rx_los_low(3),
+ pcs3_rx_pclk => clk_rx_full(3),
+ pcs3_rx_pcs_rst_c => rx_pcs_rst(3),
+ pcs3_rx_pwrup_c => '1',
+ pcs3_rxrefclk => CLK_INTERNAL_FULL,
+ pcs3_rx_serdes_rst_c => rx_serdes_rst(3),
+ pcs3_serdes_rst_dual_c => '0',
+ pcs3_signal_detect_c => '0',
+ pcs3_txdata => tx_data(3),
+ pcs3_tx_disp_sel(0) => '0',
+ pcs3_tx_force_disp(0) => '0',
+ pcs3_tx_idle_c => '0',
+ pcs3_tx_k(0) => tx_k(3),
+ pcs3_tx_pclk => clk_tx_full(3),
+ pcs3_tx_pcs_rst_c => tx_pcs_rst(3),
+ pcs3_tx_pwrup_c => '1',
+ pcs3_tx_serdes_rst_c => '0',
+
+ pcs_sci_en => reset_n,
+ pcs_sci_sel => sci_ch_i(0),
+ pcs1_sci_addr => sci_addr_i,
+ pcs1_sci_en_dual => reset_n,
+ pcs1_sci_en => reset_n,
+ pcs1_sci_int => open,
+ pcs1_sci_rddata => sci_data_out_i(7 downto 0),
+ pcs1_sci_rd => sci_read_i,
+ pcs1_sci_sel_dual => sci_ch_i(4),
+ pcs1_sci_sel => sci_ch_i(1),
+ pcs1_sci_wrdata => sci_data_in_i,
+ pcs1_sci_wrn => sci_write_i,
+ pcs2_sci_addr => sci_addr_i,
+ pcs2_sci_en_dual => reset_n,
+ pcs2_sci_en => reset_n,
+ pcs2_sci_int => open,
+ pcs2_sci_rddata => open,
+ pcs2_sci_rd => sci_read_i,
+ pcs2_sci_sel_dual => sci_ch_i(4),
+ pcs2_sci_sel => sci_ch_i(2),
+ pcs2_sci_wrdata => sci_data_in_i,
+ pcs2_sci_wrn => sci_write_i,
+ pcs3_sci_en => reset_n,
+ pcs3_sci_sel => sci_ch_i(3),
+
+
+ pcs1_cyawstn => '0',
+ pcs1_pll_refclki => CLK_REF_FULL,
+ pcs1_serdes_pdb => '1',
+ pcs2_serdes_pdb => '1',
+ pcs2_cyawstn => '0',
+ pcs3_pll_refclki => CLK_REF_FULL
+ );
+
+
+gen_channels : for i in 0 to 2 generate
THE_MED_CONTROL : entity work.med_sync_control
generic map(
IS_SYNC_SLAVE => IS_SYNC_SLAVE(i),
CLEAR => CLEAR,
SFP_LOS => SD_LOS_IN(i),
- TX_LOL => tx_pll_lol(i),
+ TX_LOL => tx_pll_lol,
RX_CDR_LOL => rx_cdr_lol(i),
RX_LOS => rx_los_low(i),
WA_POSITION => x"0",
MEDIA_MED2INT => MEDIA_MED2INT(i),
MEDIA_INT2MED => MEDIA_INT2MED(i),
- TX_DATA => tx_data(i*8-1 downto i*8),
+ TX_DATA => tx_data(i),
TX_K => tx_k(i),
- RX_DATA => rx_data(i*8-1 downto i*8),
+ RX_DATA => rx_data(i),
RX_K => rx_k(i),
- TX_DLM_WORD => TX_DLM_WORD(i*8-1 downto i*8),
- TX_DLM => TX_DLM(i),
- RX_DLM_WORD => RX_DLM_WORD(i*8-1 downto i*8),
- RX_DLM => RX_DLM(i),
+ TX_DLM_WORD => open, --TX_DLM_WORD(i*8+7 downto i*8),
+ TX_DLM => open, --TX_DLM(i),
+ RX_DLM_WORD => open, --RX_DLM_WORD(i*8+7 downto i*8),
+ RX_DLM => open, --RX_DLM(i),
SERDES_RX_READY_IN => rx_ready(i),
SERDES_TX_READY_IN => tx_ready(i),
- STAT_TX_CONTROL => stat_tx_control_i(i*32-1 downto i*32),
- STAT_RX_CONTROL => stat_rx_control_i(i*32-1 downto i*32),
- DEBUG_TX_CONTROL => debug_tx_control_i(i*32-1 downto i*32),
- DEBUG_RX_CONTROL => debug_rx_control_i(i*32-1 downto i*32),
- STAT_RESET => stat_fsm_reset_i(i*32-1 downto i*32),
- DEBUG_OUT => debug_med_sync_control_i(i*32-1 downto i*32)
+ STAT_TX_CONTROL => stat_tx_control_i(i*32+31 downto i*32),
+ STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32),
+ DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32),
+ DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
+ STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32),
+ DEBUG_OUT => debug_med_sync_control_i(i*32+31 downto i*32)
);
-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0);
-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0);
-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
-- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0);
- STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0);
- STAT_DEBUG(7 downto 4) <= rx_los_low(0) & lsm_status(0) & rx_cdr_lol(0) & tx_pll_lol(0);
+-- -- -- STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0);
+-- -- -- STAT_DEBUG(7 downto 4) <= rx_los_low(0) & lsm_status(0) & rx_cdr_lol(0) & tx_pll_lol;
-- STAT_DEBUG(9) <= CLK_REF_FULL;
-- STAT_DEBUG(10) <= clk_rx_full;
-- STAT_DEBUG(11) <= clk_tx_full;
- stat_med(i*32+0) <= rst_qd;
- stat_med(i*32+1) <= rx_pcs_rst;
- stat_med(i*32+2) <= tx_pcs_rst;
- stat_med(i*32+3) <= rx_serdes_rst;
+ stat_med(i*32+0) <= rst_qd(i);
+ stat_med(i*32+1) <= rx_pcs_rst(i);
+ stat_med(i*32+2) <= tx_pcs_rst(i);
+ stat_med(i*32+3) <= rx_serdes_rst(i);
stat_med(i*32+4) <= tx_pll_lol;
- stat_med(i*32+5) <= rx_cdr_lol;
- stat_med(i*32+6) <= rx_los_low;
- stat_med(i*32+7) <= rx_ready;
- stat_med(i*32+8) <= tx_ready;
- stat_med(i*32+9) <= lsm_status;
+ stat_med(i*32+5) <= rx_cdr_lol(i);
+ stat_med(i*32+6) <= rx_los_low(i);
+ stat_med(i*32+7) <= rx_ready(i);
+ stat_med(i*32+8) <= tx_ready(i);
+ stat_med(i*32+9) <= lsm_status(i);
stat_med(i*32+31 downto i*32+10) <= (others => '0');
end generate;
-THE_SCI_READER : entity work.sci_reader
- port map(
- CLK => SYSCLK,
- RESET => RESET,
-
- --SCI
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i,
- SCI_SEL => sci_ch_i,
- SCI_RD => sci_read_i,
- SCI_WR => sci_write_i,
-
- WA_POS_OUT => wa_position,
-
- --Slowcontrol
- BUS_RX => BUS_RX,
- BUS_TX => BUS_TX,
-
- MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
- MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
- MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
- MEDIA_STATUS_REG_IN(223 downto 96) => stat_med,
- MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'),
- DEBUG_OUT => open
- );
+-- THE_SCI_READER : entity work.sci_reader
+-- port map(
+-- CLK => SYSCLK,
+-- RESET => RESET,
+--
+-- --SCI
+-- SCI_WRDATA => sci_data_in_i,
+-- SCI_RDDATA => sci_data_out_i,
+-- SCI_ADDR => sci_addr_i,
+-- SCI_SEL => sci_ch_i,
+-- SCI_RD => sci_read_i,
+-- SCI_WR => sci_write_i,
+--
+-- WA_POS_OUT => wa_position,
+--
+-- --Slowcontrol
+-- BUS_RX => BUS_RX,
+-- BUS_TX => BUS_TX,
+--
+-- MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
+-- MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
+-- MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
+-- MEDIA_STATUS_REG_IN(223 downto 96) => stat_med,
+-- MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'),
+-- DEBUG_OUT => open
+-- );
end architecture;
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