added first MVD roc register

diff --git a/web/htdocs/index.html b/web/htdocs/index.html
index 44c7b872b7e08ffbc2fd38b42427326c34760ae5..908f42cfa8be097b6596d30680a1662852008483 100755 (executable)
--- a/web/htdocs/index.html
+++ b/web/htdocs/index.html
@@ -73,7 +73,8 @@ The main documentation of the network can be found in these two documents:
 <ul>
 <li><a href="tdc/tdcstatctrl.pl">TDC (xml-based)</a>
 <li><a href="nxyter/index.pl">Nxyter Read-out</a>
-<li><a href="jtag/index.pl">MVD Jtag Controller</a>
+<li><a href="mvd/jtag.pl">MVD Jtag Controller</a>
+<li><a href="mvd/roc.pl">MVD read-out Controller</a>
 <li><a href="network/generic.pl">Everything else</a>
 </ul>
 </div>

diff --git a/web/htdocs/jtag/index.pl b/web/htdocs/mvd/jtag.pl
similarity index 100%
rename from web/htdocs/jtag/index.pl
rename to web/htdocs/mvd/jtag.pl

diff --git a/web/htdocs/mvd/roc.pl b/web/htdocs/mvd/roc.pl
new file mode 100644 (file)
index 0000000..946dbc7
--- /dev/null
+++ b/web/htdocs/mvd/roc.pl
@@ -0,0 +1,30 @@
+&htsponse(200, "OK");
+print "Content-type: text/html\r\n\r\n";
+
+
+use CGI ':standard';
+use XML::LibXML;
+use POSIX;
+use CGI::Carp qw(fatalsToBrowser);
+
+use lib qw|../commands htdocs/commands|;
+use xmlpage;
+
+my $page;
+
+$page->{title} = "MVD Read-out Controller Register";
+$page->{link}  = "../";
+
+my @setup;
+$setup[0]->{name}    = "Status";
+$setup[0]->{cmd}     = "Mvd-0xfe4d-Status";
+$setup[0]->{period}  = 5000;
+
+xmlpage::initPage(\@setup,$page);
+ 
+
+ 
+
+1;
+
+

diff --git a/xml-db/database/Mvd.xml b/xml-db/database/Mvd.xml
new file mode 100644 (file)
index 0000000..32e1a4d
--- /dev/null
+++ b/xml-db/database/Mvd.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0"  encoding="utf-8" ?>
+<TrbNetEntity xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+              xsi:noNamespaceSchemaLocation="../schema/TrbNetEntity.xsd"
+              name="Mvd"
+              address="8000"
+              >
+  <description>Registers for the MVD ROC</description>
+
+  <!-- this is just a very minimal version -->
+  <group name="RocStatus"
+         address="0000"  size="4"  purpose="status"  mode="r"  continuous="true">
+
+    <register name="RocInput" address="0000" purpose="status">
+      <description>Status information of the ROC input buffer</description>
+      <field name="FifoEmpty" start="0" bits="1" format="boolean" >
+        <description>The input data fifo is empty</description>
+      </field>
+      <field name="FifoAlmostFull" start="1" bits="1" format="boolean" errorflag="true" >
+        <description>The input data fifo is almost full</description>
+      </field>
+      <field name="FifoFull" start="2" bits="1" format="boolean" errorflag="true" >
+        <description>The input data fifo is full</description>
+      </field>
+      <field name="DataOut" start="4" bits="2" format="binary" >
+        <description>The input data lines after the fifo</description>
+      </field>
+      <field name="DataValid" start="7" bits="1" format="boolean" >
+        <description>The input data is valid</description>
+      </field>
+      <field name="ClockActive" start="11" bits="1" format="boolean" invertflag="true" errorflag="true" >
+        <description>The input clock is active</description>
+      </field>
+      <field name="ClockCounter" start="11" bits="4" format="unsigned"  >
+        <description>Counter to check activity of the input data clock</description>
+      </field>
+      <field name="ToggleFF" start="16" bits="1" format="bitmask"  >
+        <description>Toggle Flipflop monitoring changes on the input data clock</description>
+      </field>
+      
+    </register>
+  </group>
+
+</TrbNetEntity>
+
+<!--
+  STATUS(15 downto  0) <= sr0;
+  STATUS(31 downto 16) <= sr1;
+  STATUS(47 downto 32) <= buf_data_0;
+  STATUS(63 downto 48) <= buf_data_1;
+  
+  STATUS(67 downto 64) <= "000" & buf_dataready;
+  STATUS(71 downto 68) <= std_logic_vector(pos);
+  STATUS(75 downto 72) <= "00" & start & run; 
+  STATUS(79 downto 76) <= trailer_too_late & "0" & header_detected & trailer_detected;
+  STATUS(95 downto 80) <= std_logic_vector(wait_cycles);
+  
+  -->

diff --git a/xml-db/schema/TrbNetCommon.xsd b/xml-db/schema/TrbNetCommon.xsd
index d669b0d12ba8c432aac78e321792f1e804c64572..8986c6ede399ec4502e8a19097aace10d03437c4 100644 (file)
--- a/xml-db/schema/TrbNetCommon.xsd
+++ b/xml-db/schema/TrbNetCommon.xsd
@@ -64,6 +64,7 @@
       <xs:enumeration value="unsigned"/>
       <xs:enumeration value="hex"/>
       <xs:enumeration value="bitmask"/>
+      <xs:enumeration value="binary"/>
       <xs:enumeration value="boolean"/>
       <xs:enumeration value="time"/>
       <xs:enumeration value="string"/>