--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.config.all;
+
+
+entity cbm_rich_calib is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ CRI_CAL_ACTIVE : in std_logic;
+
+ CRI_APL_DATA_IN : in std_logic_vector(15 downto 0);
+ CRI_APL_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ CRI_APL_DATAREADY_IN : in std_logic;
+ CRI_CALIB_EOD_IN : in std_logic;
+
+ CRI_APL_DATA_OUT : out std_logic_vector(15 downto 0);
+ CRI_APL_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ CRI_APL_DATAREADY_OUT : out std_logic;
+ CRI_CALIB_EOD_OUT : out std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+architecture cbm_rich_calib_arch of cbm_rich_calib is
+
+ type calib_check_states_t is (IDLE, TRIGGER_CODE, TRIGGER_NUM, COMBINER_LENGTH, COMBINER_ADDRESS, DIRICH_LENGTH, DIRICH_ADDRESS, TDC_DATA_H, TDC_DATA_L, CTS_H, CTS_L, TERMINATE, CLEANUP);
+ signal calib_current_state, calib_next_state : calib_check_states_t;
+
+ type calib_send_out_states_t is (IDLE, SECOND);
+ signal calib_out_state : calib_send_out_states_t;
+
+ signal trigger_num_i, trigger_code_i : std_logic_vector(15 downto 0);
+ signal combiner_length_i, combiner_addr_i : std_logic_vector(15 downto 0);
+ signal dirich_length_i, dirich_addr_i : std_logic_vector(15 downto 0);
+ signal dirich_length_input_i : std_logic_vector(15 downto 0);
+ signal data_h : std_logic_vector(15 downto 0);
+ signal data_full, cal_data_out : std_logic_vector(31 downto 0);
+ signal pack_num_h : std_logic_vector( 2 downto 0);
+ signal pack_num_full : std_logic_vector( 5 downto 0);
+ signal cal_eod_h : std_logic;
+ signal cal_eod_full : std_logic_vector( 1 downto 0);
+ signal data_rdy, cal_ready_out : std_logic;
+ signal dtype, cal_type_out : std_logic_vector( 3 downto 0);
+ signal dinfo_in, dinfo_out : std_logic_vector( 7 downto 0);
+
+ signal cri_apl_caldata_out : std_logic_vector(15 downto 0);
+ signal cri_apl_calpacknum_out : std_logic_vector( 2 downto 0);
+ signal cri_apl_caldrdy_out : std_logic;
+ signal cri_apl_caleod_out : std_logic;
+
+ signal cri_apl_caldata_out_l : std_logic_vector(15 downto 0);
+ signal cri_apl_calpacknum_out_l : std_logic_vector( 2 downto 0);
+ signal cri_apl_caldrdy_out_l : std_logic;
+ signal cri_apl_caleod_out_l : std_logic;
+
+ signal rec_state, cal_out_state_flg : std_logic_vector( 3 downto 0);
+ signal data_open_modelsim : std_logic_vector(23 downto 0);
+
+begin
+
+---------------------------------------------------------------------------
+-- Calibration of TDC DATA
+---------------------------------------------------------------------------
+
+-- THE_CALIB_CHECK_PROC : process(RESET, CLK)
+-- begin
+-- if RESET = '1' then
+-- calib_current_state <= IDLE;
+-- else
+-- if rising_edge(CLK) then
+-- calib_current_state <= calib_next_state;
+-- end if;
+-- end if;
+-- end process;
+
+ THE_CALIB_CHECK_MACHINE : process--(calib_current_state, CRI_CAL_ACTIVE, CRI_APL_DATAREADY_IN)
+ begin
+ wait until rising_edge(CLK);
+
+ if (RESET = '1') then
+ calib_current_state <= IDLE;
+ else
+ rec_state <= x"0";
+ data_rdy <= '0';
+ dtype <= x"0";
+
+ case (calib_next_state) is
+ when IDLE =>
+ rec_state <= x"1";
+ if (CRI_CAL_ACTIVE = '1') then
+ calib_next_state <= TRIGGER_CODE;
+ else
+ calib_next_state <= IDLE;
+ end if;
+
+ when TRIGGER_CODE =>
+ rec_state <= x"2";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_h <= CRI_APL_DATA_IN;
+ pack_num_h <= CRI_APL_PACKET_NUM_IN;
+ cal_eod_h <= CRI_CALIB_EOD_IN;
+ trigger_code_i <= CRI_APL_DATA_IN;
+ calib_next_state <= TRIGGER_NUM;
+ else
+ calib_next_state <= TRIGGER_CODE;
+ end if;
+
+ when TRIGGER_NUM =>
+ rec_state <= x"3";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_full <= data_h & CRI_APL_DATA_IN;
+ pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
+ cal_eod_full <= cal_eod_h & CRI_CALIB_EOD_IN;
+ data_rdy <= '1';
+ trigger_num_i <= CRI_APL_DATA_IN;
+ calib_next_state <= COMBINER_LENGTH;
+ else
+ calib_next_state <= TRIGGER_NUM;
+ end if;
+
+ when COMBINER_LENGTH =>
+ rec_state <= x"4";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_h <= CRI_APL_DATA_IN;
+ pack_num_h <= CRI_APL_PACKET_NUM_IN;
+ cal_eod_h <= CRI_CALIB_EOD_IN;
+ combiner_length_i <= CRI_APL_DATA_IN;
+ calib_next_state <= COMBINER_ADDRESS;
+ else
+ calib_next_state <= COMBINER_LENGTH;
+ end if;
+
+ when COMBINER_ADDRESS =>
+ rec_state <= x"5";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_full <= data_h & CRI_APL_DATA_IN;
+ pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
+ cal_eod_full <= cal_eod_h & CRI_CALIB_EOD_IN;
+ data_rdy <= '1';
+ combiner_addr_i <= CRI_APL_DATA_IN;
+ calib_next_state <= DIRICH_LENGTH;
+ else
+ calib_next_state <= COMBINER_ADDRESS;
+ end if;
+
+ when DIRICH_LENGTH =>
+ rec_state <= x"6";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_h <= CRI_APL_DATA_IN;
+ pack_num_h <= CRI_APL_PACKET_NUM_IN;
+ cal_eod_h <= CRI_CALIB_EOD_IN;
+ calib_next_state <= DIRICH_ADDRESS;
+ dirich_length_i <= CRI_APL_DATA_IN;
+ dirich_length_input_i <= CRI_APL_DATA_IN;
+ else
+ calib_next_state <= DIRICH_LENGTH;
+ end if;
+
+ when DIRICH_ADDRESS =>
+ rec_state <= x"7";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_full <= data_h & CRI_APL_DATA_IN;
+ pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
+ cal_eod_full <= cal_eod_h & CRI_CALIB_EOD_IN;
+ data_rdy <= '1';
+ --combiner_length_i <= std_logic_vector(unsigned(combiner_length_i) - 1);
+ if (CRI_APL_DATA_IN = combiner_addr_i) then -- CTS
+ calib_next_state <= CTS_H;
+ dirich_addr_i <= CRI_APL_DATA_IN; -- include CTS to calibration
+ else
+ calib_next_state <= TDC_DATA_H;
+ dirich_addr_i <= CRI_APL_DATA_IN;
+ end if;
+ else
+ calib_next_state <= DIRICH_ADDRESS;
+ end if;
+
+ when TDC_DATA_H =>
+ rec_state <= x"8";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_h <= CRI_APL_DATA_IN;
+ pack_num_h <= CRI_APL_PACKET_NUM_IN;
+ cal_eod_h <= CRI_CALIB_EOD_IN;
+ calib_next_state <= TDC_DATA_L;
+ else
+ calib_next_state <= TDC_DATA_H;
+ end if;
+
+ when TDC_DATA_L =>
+ rec_state <= x"9";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_full <= data_h & CRI_APL_DATA_IN;
+ pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
+ cal_eod_full <= cal_eod_h & CRI_CALIB_EOD_IN;
+ data_rdy <= '1';
+ dtype <= x"4";
+ if (dirich_length_i = x"0001") then
+ if (dirich_addr_i = x"5555") then
+ dtype <= x"0";
+ calib_next_state <= TERMINATE;
+ else
+ calib_next_state <= DIRICH_LENGTH;
+ end if;
+ else
+ calib_next_state <= TDC_DATA_H;
+ dirich_length_i <= std_logic_vector(unsigned(dirich_length_i) - 1);
+ --combiner_length_i <= std_logic_vector(unsigned(combiner_length_i) - 1);
+ end if;
+ else
+ calib_next_state <= TDC_DATA_L;
+ end if;
+
+ when CTS_H =>
+ rec_state <= x"A";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_h <= CRI_APL_DATA_IN;
+ pack_num_h <= CRI_APL_PACKET_NUM_IN;
+ cal_eod_h <= CRI_CALIB_EOD_IN;
+ calib_next_state <= CTS_L;
+ else
+ calib_next_state <= CTS_H;
+ end if;
+
+ when CTS_L =>
+ rec_state <= x"B";
+ if (CRI_APL_DATAREADY_IN = '1') then
+ data_full <= data_h & CRI_APL_DATA_IN;
+ pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
+ cal_eod_full <= cal_eod_h & CRI_CALIB_EOD_IN;
+ data_rdy <= '1';
+ if (dirich_length_i = x"0001") then
+ --if (combiner_length_i = x"0001")
+ calib_next_state <= DIRICH_LENGTH;
+ else
+ if ((INCLUDE_TDC = c_YES) and
+ (
+ (dirich_length_i = dirich_length_input_i) or
+ (dirich_length_i = std_logic_vector(unsigned(combiner_length_i) - 1))
+ )
+ ) then
+ dtype <= x"4";
+ end if;
+ calib_next_state <= CTS_H;
+ dirich_length_i <= std_logic_vector(unsigned(dirich_length_i) - 1);
+ combiner_length_i <= std_logic_vector(unsigned(combiner_length_i) - 1);
+ end if;
+ else
+ calib_next_state <= CTS_L;
+ end if;
+
+ when TERMINATE =>
+ rec_state <= x"C";
+ calib_next_state <= CLEANUP; --CLOSE;
+
+
+ when CLEANUP =>
+ rec_state <= x"D";
+ if (CRI_CAL_ACTIVE = '0') then
+ calib_next_state <= IDLE;
+ else
+ calib_next_state <= CLEANUP;
+ end if;
+
+ when others => calib_next_state <= IDLE;
+
+ end case;
+ end if;
+ end process;
+
+
+ dinfo_in <= cal_eod_full & pack_num_full;
+
+ THE_TDC_CAL : entity work.TDC_Calibration
+ generic map(
+ IS_COMBINER => c_NO,
+ USE_STAT_BITS => c_YES,
+ USE_DATA_WRITE => c_NO,
+ USE_DATA_FINISHED => c_NO,
+ USE_BUSY_RELEASE => c_NO
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+
+ DIN => data_full,
+ DIN_info( 7 downto 0) => dinfo_in,
+ DIN_info(31 downto 8) => (others => '0'),
+ DIN_TYPE => dtype,
+ DIN_READY => data_rdy,
+ DIN_STAT => (others => '0'),
+ FPGA_in => dirich_addr_i,
+ TRIGG_TYPE => trigger_code_i(11 downto 8),
+
+ DOUT => cal_data_out,
+ DOUT_TYPE => cal_type_out,
+ DOUT_READY => cal_ready_out,
+ DOUT_info( 7 downto 0) => dinfo_out,
+ DOUT_info(31 downto 8) => data_open_modelsim,
+ DOUT_STAT => open,
+
+ BUS_RX => BUS_RX,
+ BUS_TX => BUS_TX
+ );
+
+ THE_CALIB_OUT : process
+ begin
+ wait until rising_edge(CLK);
+ if RESET = '1' then
+ calib_out_state <= IDLE;
+ cri_apl_caldrdy_out <= '0';
+ else
+
+ case (calib_out_state) is
+ when IDLE =>
+ cal_out_state_flg <= x"1";
+ if (cal_ready_out = '1') then
+ cri_apl_caldata_out <= cal_data_out(31 downto 16);
+ cri_apl_caldata_out_l <= cal_data_out(15 downto 0);
+ cri_apl_calpacknum_out <= dinfo_out(5 downto 3);
+ cri_apl_calpacknum_out_l <= dinfo_out(2 downto 0);
+ cri_apl_caldrdy_out <= '1';
+ cri_apl_caldrdy_out_l <= '1';
+ cri_apl_caleod_out <= dinfo_out(7);
+ cri_apl_caleod_out_l <= dinfo_out(6);
+ calib_out_state <= SECOND;
+ else
+ calib_out_state <= IDLE;
+ cri_apl_caldrdy_out <= '0';
+ cri_apl_caldrdy_out_l <= '0';
+ cri_apl_caleod_out <= '0';
+ cri_apl_caleod_out_l <= '0';
+ end if;
+
+ when SECOND =>
+ cal_out_state_flg <= x"2";
+
+ cri_apl_caldata_out <= cri_apl_caldata_out_l;
+ cri_apl_calpacknum_out <= cri_apl_calpacknum_out_l;
+ cri_apl_caldrdy_out <= cri_apl_caldrdy_out_l;
+ cri_apl_caleod_out <= cri_apl_caleod_out_l;
+
+ calib_out_state <= IDLE;
+
+ when others => calib_out_state <= IDLE;
+
+ end case;
+ end if;
+ end process;
+
+ CRI_APL_DATA_OUT <= cri_apl_caldata_out;
+ CRI_APL_PACKET_NUM_OUT <= cri_apl_calpacknum_out;
+ CRI_APL_DATAREADY_OUT <= cri_apl_caldrdy_out;
+ CRI_CALIB_EOD_OUT <= cri_apl_caleod_out;
+
+end architecture;
FEE_BUSY_IN : in std_logic;
FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
+ BUS_CALIBRATON_RX : in CTRLBUS_RX;
+ BUS_CALIBRATON_TX : out CTRLBUS_TX;
+
DEBUG_OUT : out std_logic_vector(191 downto 0)
);
end entity;
type save_states_t is (IDLE, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SEND_TERM_PULSE, CLOSE, CLEANUP);
signal save_current_state, save_next_state : save_states_t;
- type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP);
+ type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_CALIB, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP);
signal send_state_current, send_state_next : data_sender_states_t;
constant loc_buff_depth : integer := 4;
type loc_buffer_dbg_t is array (0 to 7) of std_logic_vector(15 downto 0);
signal local_buffer_dbg : loc_buffer_dbg_t := (others => (others=> '0'));
+
+ signal calib_finished, cri_calib_eod, calib_active : std_logic;
+ signal cri_apl_data_2api : std_logic_vector(15 downto 0);
+ signal cri_apl_packet_num_2api : std_logic_vector(2 downto 0);
+ signal cri_apl_dataready_2api : std_logic;
+
begin
CTS_LENGTH_OUT <= (others => '0');
end process;
- SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(8),data_trans_finished,received_answer,cri_apl_run)
+ SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(16),calib_finished,data_trans_finished,received_answer,cri_apl_run)
begin
send_state_bits <= x"0";
case send_state_current is
when LOAD =>
send_state_bits <= x"3";
- if ((eod_out = '1' and df_rdy = '1') or ( local_buf_empty = '0' and local_buffer(0)(8) = '1' )) then --last word of subevent is currently in data_out
- send_state_next <= FINISH_SEND;
+ if ((eod_out = '1' and df_rdy = '1') or ( local_buf_empty = '0' and local_buffer(0)(16) = '1' )) then --last word of subevent is currently in data_out
+ send_state_next <= FINISH_CALIB;
else
send_state_next <= LOAD;
end if;
+ when FINISH_CALIB =>
+ send_state_bits <= x"4";
+ if calib_finished = '1' then
+ send_state_next <= FINISH_SEND;
+ else
+ send_state_next <= FINISH_CALIB;
+ end if;
+
when FINISH_SEND =>
send_state_bits <= x"4";
if data_trans_finished = '1' then
DATA_TRANSPORT_PROC : process
variable loc_tmp_data : std_logic_vector(15 downto 0);
variable loc_data_rdy : std_logic;
+ variable loc_eod : std_logic;
--variable pos_cnt : std_logic := '0';
begin
wait until rising_edge(CLK);
cri_apl_dataready <= '0';
data_trans_finished <= '0';
+ cri_calib_eod <= '0';
+ calib_active <= '0';
if RESET = '1' then
loc_tmp_data := x"0000";
loc_data_rdy := '0';
+ loc_eod := '0';
loaded_bytes <= (others => '0');
+ calib_active <= '0';
else
--prepare data
loc_data_rdy := '0';
if (local_buf_empty = '0') then
loc_tmp_data := local_buffer(0)(15 downto 0);
loc_data_rdy := '1';
+ loc_eod := local_buffer(0)(16);
else
loc_tmp_data := data_out;
loc_data_rdy := df_rdy;
+ loc_eod := eod_out;
end if;
end if;
if (send_state_current = LOAD) then -- or (send_state_current = FINISH_SEND)) then
if loc_data_rdy = '1' then -- only process if data is valid/rdy
- cri_apl_dataready <= '1';
- cri_packet_num_cnt <= cri_packet_num_cnt + 1;
- loaded_bytes <= loaded_bytes + 1;
+ cri_apl_dataready <= '1';
+ cri_packet_num_cnt <= cri_packet_num_cnt + 1;
+ loaded_bytes <= loaded_bytes + 1;
cri_apl_data <= loc_tmp_data;-- & tmp_data; --maybe wrong order!
cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
+ cri_calib_eod <= loc_eod;
end if; -- end data rdy
end if;-- load state
+ if ((send_state_current = LOAD) or (send_state_current = FINISH_CALIB)) then -- running hte calibration
+ calib_active <= '1';
+ end if;
-- finish the send process:
-- packet if last word in LOAD was not send, send it now.
if (send_state_current = FINISH_SEND) then
if (cri_packet_num_cnt = "00") then
data_trans_finished <= '1';
- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
+ cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
else
cri_packet_num_cnt <= cri_packet_num_cnt + 1;
cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
else
if ((send_state_current = PREPARE_SEND) or
(send_state_current = LOAD) or
+ (send_state_current = FINISH_CALIB)or
(send_state_current = FINISH_SEND) --or
--(send_state_current = STOP_SEND)
)
end if;
end if;
end process;
-
+
+ --gen_onlineDataCal: if (INCLUDE_CALIBRATION = c_YES) generate
+
+ THE_DATA_CALIBRATION : entity work.cbm_rich_calib
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ CRI_CAL_ACTIVE => calib_active,
+
+ CRI_APL_DATA_IN => cri_apl_data,
+ CRI_APL_PACKET_NUM_IN => cri_apl_packet_num,
+ CRI_APL_DATAREADY_IN => cri_apl_dataready,
+ CRI_CALIB_EOD_IN => cri_calib_eod,
+
+ CRI_APL_DATA_OUT => cri_apl_data_2api,
+ CRI_APL_PACKET_NUM_OUT => cri_apl_packet_num_2api,
+ CRI_APL_DATAREADY_OUT => cri_apl_dataready_2api,
+ CRI_CALIB_EOD_OUT => calib_finished,
+
+ BUS_RX => BUS_CALIBRATON_RX,
+ BUS_TX => BUS_CALIBRATON_TX
+ );
+ --end generate
+
+-- gen_no_onlineDataCal: if (INCLUDE_CALIBRATION = c_NO) generate
+--
+-- cri_apl_data_2api <= cri_apl_data;
+-- cri_apl_packet_num_2api <= cri_apl_packet_num;
+-- cri_apl_dataready_2api <= cri_apl_dataready;
+-- calib_finished <= '1';
+--
+-- end generate
+
-- Data to CRI board
- API_DATA_OUT <= cri_apl_data;
- API_PACKET_NUM_OUT <= cri_apl_packet_num;
- API_DATAREADY_OUT <= cri_apl_dataready;
+ API_DATA_OUT <= cri_apl_data_2api;
+ API_PACKET_NUM_OUT <= cri_apl_packet_num_2api;
+ API_DATAREADY_OUT <= cri_apl_dataready_2api;
cri_apl_reading <= API_READ_IN;
API_SHORT_TRANSFER_OUT <= '0';
DEBUG_OUT( 9) <= df_full_real;
DEBUG_OUT(10) <= df_afull;
DEBUG_OUT(11) <= '0';
- DEBUG_OUT(14 downto 12) <= cri_apl_packet_num;
+ DEBUG_OUT(14 downto 12) <= cri_apl_packet_num_2api;
DEBUG_OUT(15) <= '0';
DEBUG_OUT(31 downto 16) <= cri_event_cnt;
jspc29 / cri.git / commitdiff