\hline
Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\
\hline \hline
- \multirow{13}{*}{0xc800} & \multirow{13}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
+ \multirow{14}{*}{0xc800} & \multirow{14}{*}{Basic controls} & 3-0
+& Enables different signals to the HPLA* output for debugging with logic
+analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
& & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
& & 7-5 & reserved.\\
& & 8 & Resets the internal counters (active high).\\
& & 11-9 & reserved.\\
& & 12 & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
- & & 31-13 & reserved.\\
+ & & 27-13 & reserved.\\
+ & & 31-28
+& Used to divide the calibration hit frequency.\\&&& $Freq_{hit}=1.6~MHz/2^n$\\
+
+
\hline
\multirow{10}{*}{0xc801} & \multirow{10}{*}{Trigger window} & 10-0 & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
& & 15-11 & reserved.\\