###################################################################################
#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
+my $BasePath = "../base/"; #path to "base" directory
my $lattice_path = '/d/sugar/lattice/diamond/1.3';
my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/';
my $lm_license_file_for_synplify = "27000\@localhost";
my $FAMILYNAME="LatticeECP3";
my $DEVICENAME="LFE3-150EA";
my $PACKAGE="FPBGA1156";
-my $SPEEDGRADE="7";
+my $SPEEDGRADE="8";
#create full lpf file
-system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf");
system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
#set -e
my $FAMILYNAME="LatticeECP3";
my $DEVICENAME="LFE3-150EA";
my $PACKAGE="FPBGA1156";
-my $SPEEDGRADE="7";
+my $SPEEDGRADE="8";
#create full lpf file
my $FAMILYNAME="LatticeECP3";
my $DEVICENAME="LFE3-150EA";
my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="7";
+my $SPEEDGRADE="8";
#create full lpf file
my $FAMILYNAME="LatticeECP3";
my $DEVICENAME="LFE3-150EA";
my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="7";
+my $SPEEDGRADE="8";
#create full lpf file
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 200 MHz;
+ FREQUENCY PORT CLK_EXT_3 10 MHz;
+ FREQUENCY PORT CLK_EXT_4 10 MHz;
+
#################################################################
# Clock I/O
set_option -technology LATTICE-ECP3
set_option -part LFE3_150EA
set_option -package FN1156C
-set_option -speed_grade -7
+set_option -speed_grade -8
set_option -part_companion ""
# compilation/mapping options
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib "work" "./trb3_central.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45
CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK
CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200 MHz <-- for Serdes if GPLL doesn't work. Same oscillator as GPLL left!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200 MHz <-- use this clock for BASIC tests!
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
FLASH_CS : out std_logic;
FLASH_CIN : out std_logic;
FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
+ PROGRAMN : out std_logic := '1'; --reboot FPGA
--Misc
ENPIRION_CLOCK : out std_logic; --Clock for power supply, not necessary, floating
---------------------------------------------------------------------------
-- FPGA communication
---------------------------------------------------------------------------
- FPGA1_COMM <= (others => '0');
- FPGA2_COMM <= (others => '0');
- FPGA3_COMM <= (others => '0');
- FPGA4_COMM <= (others => '0');
+ FPGA1_COMM <= (others => 'Z');
+ FPGA2_COMM <= (others => 'Z');
+ FPGA3_COMM <= (others => 'Z');
+ FPGA4_COMM <= (others => 'Z');
- FPGA1_TTL <= (others => '0');
- FPGA2_TTL <= (others => '0');
- FPGA3_TTL <= (others => '0');
- FPGA4_TTL <= (others => '0');
+ FPGA1_TTL <= (others => 'Z');
+ FPGA2_TTL <= (others => 'Z');
+ FPGA3_TTL <= (others => 'Z');
+ FPGA4_TTL <= (others => 'Z');
- FPGA1_CONNECTOR <= (others => '0');
- FPGA2_CONNECTOR <= (others => '0');
- FPGA3_CONNECTOR <= (others => '0');
- FPGA4_CONNECTOR <= (others => '0');
+ FPGA1_CONNECTOR <= (others => 'Z');
+ FPGA2_CONNECTOR <= (others => 'Z');
+ FPGA3_CONNECTOR <= (others => 'Z');
+ FPGA4_CONNECTOR <= (others => 'Z');
---------------------------------------------------------------------------
FLASH_CLK <= '0';
FLASH_CS <= '0';
FLASH_CIN <= '0';
-
+ PROGRAMN <= '1';
---------------------------------------------------------------------------
-- Big AddOn Connector
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 100 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
#################################################################
# Clock I/O
set_option -technology LATTICE-ECP3
set_option -part LFE3_150EA
set_option -package FN672C
-set_option -speed_grade -7
+set_option -speed_grade -8
set_option -part_companion ""
# compilation/mapping options
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib "work" "./trb3_periph.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
port(
--Clocks
CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
--Trigger
TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ --TDC clock is separate
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
-<Strategy version="1.0" predefined="0" description="" label="Strategy1"/>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+ <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
+</Strategy>
<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="1.3" title="trb3_central" device="LFE3-150EA-7FN672C" default_implementation="trb3_central">
+<BaliProject version="1.3" title="trb3_central" device="LFE3-150EA-7FN1156C" default_implementation="trb3_central">
<Options/>
<Implementation title="trb3_central" dir="trb3_central" description="trb3_central" default_strategy="Strategy1">
<Options/>
jspc29 / trb3.git / commitdiff