entity panda_dirc_wasa is
generic(
- PADIWA_FLAVOUR : integer := 2
+ PADIWA_FLAVOUR : integer := 2;
+ TEMP_CORRECTION: integer := 0
);
port(
CON : out std_logic_vector(16 downto 1);
CLK : in std_logic;
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
+ COMP_IN : in signed(15 downto 0);
WRITE_IN : in std_logic;
ADDR_IN : in std_logic_vector(3 downto 0);
PWM : out std_logic_vector(31 downto 0)
signal inp_invert : std_logic_vector(15 downto 0);
signal input_enable : std_logic_vector(15 downto 0);
signal inp_status : std_logic_vector(15 downto 0);
-signal led_status : std_logic_vector(4 downto 0);
+signal led_status : std_logic_vector(4 downto 0) := "10000";
signal timer : unsigned(18 downto 0) := (others => '0');
signal last_inp : std_logic_vector(3 downto 0) := (others => '0');
signal ram_fsm_write_i: std_logic;
signal enable_cfg_flash : std_logic;
+signal comp_setting : std_logic_vector(15 downto 0);
+signal compensate_i : signed(15 downto 0);
+signal temp_calc_i : signed(27 downto 0);
+signal temperature_i_s : std_logic_vector(11 downto 0);
+signal comp_setting_s : std_logic_vector(15 downto 0);
begin
CLK => clk_i,
DATA_IN => pwm_data_i,
DATA_OUT => pwm_data_o,
+ COMP_IN => compensate_i,
WRITE_IN => pwm_write_i,
ADDR_IN => pwm_addr_i,
PWM => pwm_i
when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));
when x"4" => spi_reg20_i <= inp_invert;
when x"5" => spi_reg20_i <= inp_stretch;
+ when x"6" => spi_reg20_i <= comp_setting;
when others => null;
end case;
else
when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));
when x"4" => inp_invert <= spi_data_i;
when x"5" => inp_stretch <= spi_data_i;
+ when x"6" => comp_setting <= spi_data_i;
when others => null;
end case;
end if;
inp_status <= INP_i when rising_edge(clk_i);
last_inp <= inp_status(3 downto 0) when rising_edge(clk_i);
+temperature_i_s <= temperature_i when rising_edge(clk_26);
+comp_setting_s <= comp_setting when rising_edge(clk_26);
+temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_26);
+
+gen_comp: if TEMP_CORRECTION = 1 generate
+ compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_26);
+end generate;
+gen_no_comp: if TEMP_CORRECTION = 0 generate
+ compensate_i <= (others => '0');
+end generate;
+
---------------------------------------------------------------------------
-- LED blinking when activity on inputs
DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
DATA_OUT : out std_logic_vector(15 downto 0);
WRITE_IN : in std_logic := '0';
+ COMP_IN : in signed(15 downto 0);
ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
type ram_t is array(0 to 15) of unsigned(16 downto 0);
signal set : ram_t := (others => '0' & x"87C1");
+signal set_tmp : ram_t;
type cnt_t is array(0 to 15) of unsigned(16 downto 0);
signal cnt : cnt_t := (others => (others => '0'));
flag(i) <= cnt(i)(16);
last_flag(i) <= flag(i) when rising_edge(CLK);
pwm_i(i) <= (last_flag(i) xor flag(i)) when rising_edge(CLK);
- cnt(i) <= cnt(i) + set(i) when rising_edge(CLK);
+ set_tmp(i) <= unsigned(signed(set(i)) + resize(COMP_IN,17));
+ cnt(i) <= cnt(i) + set_tmp(i) when rising_edge(CLK);
end generate;