--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3
+-- Module Version: 5.1
+--/d/jspc29/lattice/diamond/3.8_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_18x8k_oreg/fifo_18x8k_oreg.fdc
+
+-- Tue Dec 6 13:41:43 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_18x8k_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(12 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(13 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x8k_oreg;
+
+architecture Structure of fifo_18x8k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal rptr_13: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co6_1: std_logic;
+ signal co5_3: std_logic;
+ signal wcount_13: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co6_2: std_logic;
+ signal co5_4: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_3_9: std_logic;
+ signal mdout1_2_9: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_3_10: std_logic;
+ signal mdout1_2_10: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_3_11: std_logic;
+ signal mdout1_2_11: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_3_12: std_logic;
+ signal mdout1_2_12: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_3_13: std_logic;
+ signal mdout1_2_13: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_3_14: std_logic;
+ signal mdout1_2_14: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_3_15: std_logic;
+ signal mdout1_2_15: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_3_16: std_logic;
+ signal mdout1_2_16: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal rptr_12_ff2: std_logic;
+ signal rptr_11_ff2: std_logic;
+ signal mdout1_3_17: std_logic;
+ signal mdout1_2_17: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal wcount_0: std_logic;
+ signal cnt_con: std_logic;
+ signal precin: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal rptr_12: std_logic;
+ signal rptr_11: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_5: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal co6_3: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_5 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_5 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_4 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_4 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_3 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_3 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_2 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_2 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_1 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_1 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_0 : label is "fifo_18x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_0 : label is "";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_5: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_4: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_3: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_2: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb);
+
+ INV_0: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ pdp_ram_0_0_7: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8,
+ ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4,
+ ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7,
+ ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3,
+ ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i,
+ OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset,
+ DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open,
+ DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open,
+ DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open,
+ DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open,
+ DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open,
+ DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open,
+ DOB9=>open, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7,
+ DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4,
+ DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1,
+ DOB0=>mdout1_0_0);
+
+ pdp_ram_0_1_6: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15),
+ DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12),
+ DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9),
+ ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7,
+ ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3,
+ ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12,
+ CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10,
+ ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6,
+ ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2,
+ ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12,
+ CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_17,
+ DOB7=>mdout1_0_16, DOB6=>mdout1_0_15, DOB5=>mdout1_0_14,
+ DOB4=>mdout1_0_13, DOB3=>mdout1_0_12, DOB2=>mdout1_0_11,
+ DOB1=>mdout1_0_10, DOB0=>mdout1_0_9);
+
+ pdp_ram_1_0_5: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8,
+ ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4,
+ ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7,
+ ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3,
+ ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i,
+ OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset,
+ DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open,
+ DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open,
+ DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open,
+ DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open,
+ DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open,
+ DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open,
+ DOB9=>open, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7,
+ DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4,
+ DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1,
+ DOB0=>mdout1_1_0);
+
+ pdp_ram_1_1_4: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15),
+ DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12),
+ DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9),
+ ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7,
+ ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3,
+ ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12,
+ CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10,
+ ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6,
+ ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2,
+ ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12,
+ CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_17,
+ DOB7=>mdout1_1_16, DOB6=>mdout1_1_15, DOB5=>mdout1_1_14,
+ DOB4=>mdout1_1_13, DOB3=>mdout1_1_12, DOB2=>mdout1_1_11,
+ DOB1=>mdout1_1_10, DOB0=>mdout1_1_9);
+
+ pdp_ram_2_0_3: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8,
+ ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4,
+ ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7,
+ ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3,
+ ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i,
+ OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset,
+ DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open,
+ DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open,
+ DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open,
+ DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open,
+ DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open,
+ DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open,
+ DOB9=>open, DOB8=>mdout1_2_8, DOB7=>mdout1_2_7,
+ DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, DOB4=>mdout1_2_4,
+ DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, DOB1=>mdout1_2_1,
+ DOB0=>mdout1_2_0);
+
+ pdp_ram_2_1_2: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15),
+ DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12),
+ DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9),
+ ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7,
+ ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3,
+ ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12,
+ CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10,
+ ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6,
+ ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2,
+ ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12,
+ CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_17,
+ DOB7=>mdout1_2_16, DOB6=>mdout1_2_15, DOB5=>mdout1_2_14,
+ DOB4=>mdout1_2_13, DOB3=>mdout1_2_12, DOB2=>mdout1_2_11,
+ DOB1=>mdout1_2_10, DOB0=>mdout1_2_9);
+
+ pdp_ram_3_0_1: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8,
+ ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4,
+ ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>wptr_12, CSA0=>wptr_11, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7,
+ ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3,
+ ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i,
+ OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>rptr_12, CSB0=>rptr_11, RSTB=>Reset,
+ DOA17=>open, DOA16=>open, DOA15=>open, DOA14=>open,
+ DOA13=>open, DOA12=>open, DOA11=>open, DOA10=>open,
+ DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open,
+ DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>open,
+ DOB17=>open, DOB16=>open, DOB15=>open, DOB14=>open,
+ DOB13=>open, DOB12=>open, DOB11=>open, DOB10=>open,
+ DOB9=>open, DOB8=>mdout1_3_8, DOB7=>mdout1_3_7,
+ DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, DOB4=>mdout1_3_4,
+ DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, DOB1=>mdout1_3_1,
+ DOB0=>mdout1_3_0);
+
+ pdp_ram_3_1_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15),
+ DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12),
+ DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9),
+ ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7,
+ ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3,
+ ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo, CSA1=>wptr_12,
+ CSA0=>wptr_11, RSTA=>Reset, DIB17=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB15=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB12=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB9=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB6=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB3=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB0=>scuba_vlo, ADB13=>rptr_10,
+ ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6,
+ ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2,
+ ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>rptr_12,
+ CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_17,
+ DOB7=>mdout1_3_16, DOB6=>mdout1_3_15, DOB5=>mdout1_3_14,
+ DOB4=>mdout1_3_13, DOB3=>mdout1_3_12, DOB2=>mdout1_3_11,
+ DOB1=>mdout1_3_10, DOB0=>mdout1_3_9);
+
+ FF_90: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_89: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_88: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_87: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_86: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_85: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_84: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_83: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_82: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_81: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_80: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_79: FD1P3DX
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_78: FD1P3DX
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_77: FD1P3DX
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_76: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_75: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_74: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_73: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_72: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_71: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_70: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_69: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_68: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_67: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_66: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_65: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_64: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_63: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_62: FD1P3DX
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_61: FD1P3DX
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_60: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_59: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_58: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_57: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_56: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_55: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_54: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_53: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_52: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_51: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_50: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_49: FD1P3DX
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_48: FD1P3DX
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_47: FD1P3DX
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_46: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_45: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_44: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_43: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_42: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_41: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_40: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_39: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_38: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_37: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_36: FD1P3DX
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_35: FD1P3DX
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_34: FD1P3DX
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_33: FD1P3DX
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_32: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_31: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_30: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_29: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_28: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_27: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_26: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_25: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_24: FD1P3DX
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_23: FD1P3DX
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_22: FD1P3DX
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_21: FD1P3DX
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_20: FD1P3DX
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_19: FD1P3DX
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_13);
+
+ FF_18: FD1P3DX
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_17: FD1P3DX
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_16: FD1P3DX
+ port map (D=>rptr_11_ff, SP=>scuba_vhi, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff2);
+
+ FF_15: FD1P3DX
+ port map (D=>rptr_12_ff, SP=>scuba_vhi, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff2);
+
+ FF_14: FD1S3DX
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_13: FD1S3DX
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_12: FD1S3DX
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_11: FD1S3DX
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_10: FD1S3DX
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_9: FD1S3DX
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_8: FD1S3DX
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_7: FD1S3DX
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_6: FD1S3DX
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_5: FD1S3DX
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_4: FD1S3DX
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_3: FD1S3DX
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_2: FD1S3DX
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_1: FD1S3DX
+ port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+ bdcnt_bctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+ bdcnt_bctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+ bdcnt_bctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+ bdcnt_bctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+ bdcnt_bctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+ bdcnt_bctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+ bdcnt_bctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co5, S0=>ifcount_12, S1=>ifcount_13, COUT=>co6);
+
+ e_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ e_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+ e_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2,
+ B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+ e_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4,
+ B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+ e_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6,
+ B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+ e_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8,
+ B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+ e_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10,
+ B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, COUT=>co5_1);
+
+ e_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_12,
+ B1=>fcount_13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_1, S0=>open, S1=>open,
+ COUT=>cmp_le_1_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open,
+ COUT=>open);
+
+ g_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ g_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+ g_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ g_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+ g_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+ g_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+ g_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4_2, S0=>open, S1=>open, COUT=>co5_2);
+
+ g_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i,
+ B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_2, S0=>open, S1=>open,
+ COUT=>cmp_ge_d1_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open,
+ COUT=>open);
+
+ w_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+ w_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0_3);
+
+ w_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1_3);
+
+ w_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2_3);
+
+ w_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7,
+ COUT=>co3_3);
+
+ w_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9,
+ COUT=>co4_3);
+
+ w_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11,
+ COUT=>co5_3);
+
+ w_ctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_3, S0=>iwcount_12, S1=>iwcount_13,
+ COUT=>co6_1);
+
+ r_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+ r_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_4);
+
+ r_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_4);
+
+ r_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_4);
+
+ r_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7,
+ COUT=>co3_4);
+
+ r_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9,
+ COUT=>co4_4);
+
+ r_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11,
+ COUT=>co5_4);
+
+ r_ctr_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_4, S0=>ircount_12, S1=>ircount_13,
+ COUT=>co6_2);
+
+ mux_17: MUX41
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(0));
+
+ mux_16: MUX41
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(1));
+
+ mux_15: MUX41
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(2));
+
+ mux_14: MUX41
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(3));
+
+ mux_13: MUX41
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(4));
+
+ mux_12: MUX41
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(5));
+
+ mux_11: MUX41
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(6));
+
+ mux_10: MUX41
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(7));
+
+ mux_9: MUX41
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(8));
+
+ mux_8: MUX41
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(9));
+
+ mux_7: MUX41
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(10));
+
+ mux_6: MUX41
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(11));
+
+ mux_5: MUX41
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(12));
+
+ mux_4: MUX41
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(13));
+
+ mux_3: MUX41
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(14));
+
+ mux_2: MUX41
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(15));
+
+ mux_1: MUX41
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(16));
+
+ mux_0: MUX41
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(17));
+
+ precin_inst348: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000",
+ INIT0=> X"0000")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+ wcnt_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+ wcnt_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+ wcnt_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+ wcnt_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+ wcnt_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+ wcnt_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_5);
+
+ wcnt_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co5_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12, COUT=>co6_3);
+
+ wcnt_7: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co6_3, S0=>wcnt_sub_13, S1=>open,
+ COUT=>open);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_6);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open,
+ COUT=>co1_6);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open,
+ COUT=>co2_6);
+
+ af_set_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open,
+ COUT=>co3_6);
+
+ af_set_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open,
+ COUT=>co4_6);
+
+ af_set_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open,
+ COUT=>co5_6);
+
+ af_set_cmp_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
jspc29 / trbnet.git / commitdiff