SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal
SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy
DUMMY_DATA_CONFIG_IN : in std_logic_vector(15 downto 0); --11..0: number of debug words
+ DATA_WORD_LIMIT_IN : in std_logic_vector(9 downto 0);
+ HIT1_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
+ HIT0_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
+ SUPPRESS_SINGLE_HIT0_IN : in std_logic;
--Data Input from FEE
DATA_BUS_IN : in std_logic_vector(23 downto 0);
DATA_VALID_IN : in std_logic;
signal data_buffer : std_logic_vector(31 downto 0);
+ signal counter_data_i : unsigned(9 downto 0);
+ signal too_many_words_i : std_logic;
+
begin
-------------------------------------------------------------------------------
data_i(21) <= DATA_BUS_IN(11);
data_i(20 downto 11) <= (others => '0');
data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0);
- data_write_i <= DATA_VALID_IN;
+ data_write_i <= DATA_VALID_IN and not too_many_words_i;
if FINISHED_READOUT_IN = '1' then
current_state <= FINISH;
end if;
stored_hit_1 <= '0';
end if;
end if;
-
+ if too_many_words_i = '1' then
+ data_write_i <= '0';
+ end if;
if FINISHED_READOUT_IN = '1' then
- current_state <= FINISH;
+ if stored_hit_1 = '0' then
+ current_state <= FINISH;
+ else
+ data_write_i <= '1';
+ current_state <= FINISH;
+ end if;
end if;
when SEND_DUMMY =>
end if;
end process;
+-------------------------------------------------------------------------------
+-- Word Counter
+-------------------------------------------------------------------------------
+ proc_word_counter : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if current_state = IDLE then
+ counter_data_i <= (others => '0');
+ elsif DATA_VALID_IN = '1' then
+ counter_data_i <= counter_data_i + to_unsigned(1,1);
+ end if;
+ if counter_data_i >= unsigned(DATA_WORD_LIMIT_IN) then
+ too_many_words_i <= '1';
+ else
+ too_many_words_i <= '0';
+ end if;
+ end if;
+ end process;
+
+
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
DEBUG_REGISTER(8) <= SEND_DUMMY_DATA_IN;
DEBUG_REGISTER(9) <= SELECT_DATA_FORMAT_IN;
DEBUG_REGISTER(10) <= DATA_VALID_IN;
- DEBUG_REGISTER(31 downto 11) <= (others => '0');
+ DEBUG_REGISTER(11) <= too_many_words_i;
+ DEBUG_REGISTER(21 downto 12) <= std_logic_vector(counter_data_i);
+ DEBUG_REGISTER(31 downto 22) <= (others => '0');
end architecture;
COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0);
COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0);
+ STAT_REG_OUT : out std_logic_vector(63 downto 0);
CTRL_REG_IN : in std_logic_vector(63 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
signal aod_in_i : std_logic;
signal dst_in_i : std_logic;
signal rsv_in_i : std_logic;
- signal trigger_i : std_logic;
- signal trigger_timing : std_logic;
signal trigger_pseudo_timing : std_logic;
signal trigger_pseudo_tmg_long : std_logic;
signal trg_pulse_counter : unsigned(4 downto 0);
signal reg_timing_trigger : std_logic;
signal trigger_begin_run : std_logic;
- signal trigger_reg_pulse_i : std_logic;
+-- signal trigger_reg_pulse_i : std_logic;
signal reset_trigger_logic_i : std_logic;
signal reset_mbo_logic_i : std_logic;
signal last_rb_read_enable_in : std_logic;
signal readback_mem_write : std_logic;
signal readback_mem_full : std_logic;
+ signal switch_polarity : std_logic;
+ signal trigger_input_corr : std_logic;
+ signal lvl1_statusbits_i : std_logic_vector(31 downto 0);
+
+ signal data_word_limit_i : std_logic_vector(9 downto 0);
+ signal hit1_lower_limit_i : std_logic_vector(10 downto 0);
+ signal hit0_lower_limit_i : std_logic_vector(10 downto 0);
+ signal suppress_single_hit0_i : std_logic;
begin
-- Select Internal or external common stop, produce trigger signals
-------------------------------------------------------------------------------
- TRIGGER_OUT <= trigger_i;
- TRIGGER_MONITOR_OUT <= trigger_reg_pulse_i;
-
- trigger_i <= (TRIGGER_IN and cms_active_i) or trigger_pseudo_tmg_long;
- trigger_reg_pulse_i <= (trigger_timing and cms_active_i) or trigger_pseudo_timing;
-
- THE_CMS_SYNC : signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 1
- )
- port map(
- RESET => RESET,
- D_IN(0) => TRIGGER_IN,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT(0) => reg_timing_trigger
- );
-
- PULSE_TIMING_TRIGGER : edge_to_pulse
- port map (
- CLOCK => CLK,
- en_clk => '1',
- SIGNAL_IN => reg_timing_trigger,
- PULSE => trigger_timing
- );
+ TRIGGER_OUT <= ((TRIGGER_IN xor switch_polarity) and cms_active_i) or trigger_pseudo_tmg_long;
+ TRIGGER_MONITOR_OUT <= ((TRIGGER_IN xor switch_polarity)) or trigger_pseudo_tmg_long;
PULSE_PSEUDO_TIMING : process(CLK)
end process;
+
+
+---------------------------------------------------------------------
+-- Status Register
+---------------------------------------------------------------------
+
+STAT_REG_OUT(STAT_REG_OUT'left downto 0) <= (others => '0');
+
-------------------------------------------------------------------------------
-- Trigger Handler
-------------------------------------------------------------------------------
port map(
CLK => CLK,
RESET => reset_trigger_logic_i,
- TRG_BEGRUN_IN => trigger_begin_run,
--LVL1 trigger
LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN,
LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN,
LVL1_RELEASE_OUT => LVL1_RELEASE_OUT,
- LVL1_STATUSBITS_OUT => LVL1_STATUSBITS_OUT,
+ LVL1_STATUSBITS_OUT => lvl1_statusbits_i,
DO_BEGIN_RUN_IN => trigger_begin_run,
--FSM control
START_TRIGGER_OUT => start_trigger_i,
SEND_DEBUG_INFORMATION_IN => data_debug_i,
SEND_DUMMY_DATA_IN => data_dummy_i,
DUMMY_DATA_CONFIG_IN => dummy_data_config_i,
+ DATA_WORD_LIMIT_IN => data_word_limit_i,
+ HIT1_LOWER_LIMIT_IN => hit1_lower_limit_i,
+ HIT0_LOWER_LIMIT_IN => hit0_lower_limit_i,
+ SUPPRESS_SINGLE_HIT0_IN => suppress_single_hit0_i,
--Data Input from FEE
DATA_BUS_IN => data_bus_i,
DATA_VALID_IN => data_bus_valid_i,
end if;
end process;
--------------------------------------------------------------------------------
--- Readback FiFo
--------------------------------------------------------------------------------
- THE_TDC_READBACK_MEM : fifo_18x256_oreg
- port map (
- Data(7 downto 0) => add_in_i(8 downto 1),
- Data(8) => add_in_i(0),
- Data(15 downto 9) => (others => '0'),
- Data(16) => dst_in_i,
- Data(17) => aod_in_i,
- Clock => CLK,
- AmFullThresh => (others => '0'),
- WrEn => readback_mem_write,
- RdEn => RB_READ_ENABLE_IN,
- Reset => RESET,
- Q => RB_DATA_OUT(17 downto 0),
- Empty => RB_EMPTY_OUT,
- Full => readback_mem_full
- );
-
- PULSE_DEBUG_WRITE : edge_to_pulse
- port map (
- CLOCK => CLK,
- en_clk => '1',
- signal_in => dst_in_i,
- PULSE => readback_mem_write
- );
-
-
--- RB_EMPTY_OUT <= '0';
-process(CLK)
- begin
- if rising_edge(CLK) then
- last_rb_read_enable_in <= RB_READ_ENABLE_IN;
- RB_READY_OUT <= last_rb_read_enable_in;
- end if;
- end process;
- RB_DATA_OUT(31 downto 18) <= (others => '0');
-
-
+-- -------------------------------------------------------------------------------
+-- -- Readback FiFo
+-- -------------------------------------------------------------------------------
+-- THE_TDC_READBACK_MEM : fifo_18x256_oreg
+-- port map (
+-- Data(7 downto 0) => add_in_i(8 downto 1),
+-- Data(8) => add_in_i(0),
+-- Data(15 downto 9) => (others => '0'),
+-- Data(16) => dst_in_i,
+-- Data(17) => aod_in_i,
+-- Clock => CLK,
+-- AmFullThresh => (others => '0'),
+-- WrEn => readback_mem_write,
+-- RdEn => RB_READ_ENABLE_IN,
+-- Reset => RESET,
+-- Q => RB_DATA_OUT(17 downto 0),
+-- Empty => RB_EMPTY_OUT,
+-- Full => readback_mem_full
+-- );
+--
+-- PULSE_DEBUG_WRITE : edge_to_pulse
+-- port map (
+-- CLOCK => CLK,
+-- en_clk => '1',
+-- signal_in => dst_in_i,
+-- PULSE => readback_mem_write
+-- );
+--
+--
+-- -- RB_EMPTY_OUT <= '0';
+-- process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- last_rb_read_enable_in <= RB_READ_ENABLE_IN;
+-- RB_READY_OUT <= last_rb_read_enable_in;
+-- end if;
+-- end process;
+-- RB_DATA_OUT(31 downto 18) <= (others => '0');
+--
+--
-------------------------------------------------------------------------------
-- Other settings
trigger_begin_run <= COMMON_CTRL_REG_IN(22);
data_format_i <= COMMON_CTRL_REG_IN(84);
data_dummy_i <= COMMON_CTRL_REG_IN(85);
+ switch_polarity <= COMMON_CTRL_REG_IN(93);
data_debug_i <= COMMON_CTRL_REG_IN(94);
cms_active_i <= COMMON_CTRL_REG_IN(95);
end if;
end process;
+ data_word_limit_i <= std_logic_vector(to_unsigned(768,10));
+ hit1_lower_limit_i <= std_logic_vector(to_unsigned(0,11));
+ hit0_lower_limit_i <= std_logic_vector(to_unsigned(0,11));
+ suppress_single_hit0_i <= '0';
+
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
DEBUG_OUT <= debug_control_i;
+ process(lvl1_statusbits_i)
+ begin
+ LVL1_STATUSBITS_OUT <= lvl1_statusbits_i;
+ LVL1_STATUSBITS_OUT(22) <= not debug_ctrl_line_handle_i(8);
+ end process;
+
process(CLK)
begin
if rising_edge(CLK) then
SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal
SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy
DUMMY_DATA_CONFIG_IN : in std_logic_vector(15 downto 0); --11..0: number of debug words
+ DATA_WORD_LIMIT_IN : in std_logic_vector(9 downto 0);
+ HIT1_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
+ HIT0_LOWER_LIMIT_IN : in std_logic_vector(10 downto 0);
+ SUPPRESS_SINGLE_HIT0_IN : in std_logic;
--Data Input from FEE
DATA_BUS_IN : in std_logic_vector(23 downto 0);
DATA_VALID_IN : in std_logic;
COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0);
COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0);
+ STAT_REG_OUT : out std_logic_vector(63 downto 0);
CTRL_REG_IN : in std_logic_vector(63 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
CLK : in std_logic;
RESET : in std_logic;
- TRG_BEGRUN_IN : in std_logic;
--LVL1 trigger
LVL1_TRG_DATA_VALID_IN : in std_logic; --trigger type, number, code, information are valid
LVL1_VALID_TIMING_TRG_IN : in std_logic; --valid timing trigger has been received
+ component SEDAA --SED component
+ -- synthesis translate_off
+ generic (
+ OSC_DIV :string :="1" );
+ -- synthesis translate_on
+ port (
+ SEDENABLE : in std_logic;
+ SEDSTART : in std_logic;
+ SEDFRCERR : in std_logic;
+ SEDERR : out std_logic;
+ SEDDONE : out std_logic;
+ SEDINPROG : out std_logic;
+ SEDCLKOUT : out std_logic
+ );
+
+end component;
CLK : in std_logic;
RESET : in std_logic;
- TRG_BEGRUN_IN : in std_logic;
--LVL1 trigger
LVL1_TRG_DATA_VALID_IN : in std_logic; --trigger type, number, code, information are valid
LVL1_VALID_TIMING_TRG_IN : in std_logic; --valid timing trigger has been received
signal timer_clear : std_logic;
signal state_bits : std_logic_vector(3 downto 0);
-
+ signal lvl1_statusbits_i : std_logic_vector(31 downto 0);
begin
end if;
when TIMING_TRIGGER =>
- if timer = x"3F" then
+ if timer = x"02" then
current_state <= DO_READOUT;
start_readout_i <= '1';
end if;
FINISHED_READOUT_OUT <= finished_readout_i;
LVL1_RELEASE_OUT <= lvl1_release_i;
- LVL1_STATUSBITS_OUT <= (others => '0');
+ LVL1_STATUSBITS_OUT <= lvl1_statusbits_i;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or current_state = IDLE then
+ lvl1_statusbits_i <= (others => '0');
+ else
+ lvl1_statusbits_i(23) <= lvl1_statusbits_i(23) or TOKEN_MISSING_IN;
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/pll_in25_out100.vhd"
add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../trbnet/basics/pulse_stretch.vhd"
add_file -vhdl -lib work "../trbnet/special/adc_ltc2308_readout.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd"
add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd"
+add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_data.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd"
add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd"
use work.mdc_oepb_pack.all;
use work.trb_net_components.all;
use work.version.all;
+use work.lattice_ecp2m_fifo.all;
---------------------------------------------------------------------
-- 0x22 Bit 21 -> select dummy data (0: normal data, 1: dummy data)
-- 0x22 Bit 30 -> select debug output (0: off, 1: on)
--
+-- 0x80 15-0 -> trigger edge count
+-- 0x80 23-16 -> trigger length
-- 0xc0 0x0010 -> select short
-- 0xc0 0x0020 -> select long
+-- 0xc0 0x8000 -> switch trigger polarity
-- 0xc1 0x0ABC0000 -> x"ABC" number of test data words
---------------------------------------------------------------------
---------------------------------------------------------------------
entity mdc_oepb is
generic(
- REGIO_NUM_STAT_REGS : integer := 4;
+ REGIO_NUM_STAT_REGS : integer := 1;
REGIO_NUM_CTRL_REGS : integer := 1
);
port(
--Read back data from TDC
signal readback_mem_read : std_logic;
- signal readback_mem_write : std_logic;
signal readback_mem_empty : std_logic;
signal readback_mem_ready : std_logic;
signal readback_mem_data_out : std_logic_vector(31 downto 0);
+ signal readback_mem_write : std_logic;
+ signal last_rb_read_enable_in : std_logic;
+ signal readback_mem_write_handler : std_logic;
+ signal readback_mem_full : std_logic;
+ signal rb_fifo_input : std_logic_vector(17 downto 0);
+ signal last_rb_fifo_input : std_logic_vector(17 downto 0);
+
--Status Registers
signal statreg_read : std_logic;
signal statreg_data : std_logic_vector(31 downto 0);
signal debug_mdc_control_i : std_logic_vector(31 downto 0);
+ signal debug_lvl1_handler : std_logic_vector(15 downto 0);
+
+ signal sederr_i : std_logic;
+ signal seddone_i : std_logic;
+ signal sedinprog_i : std_logic;
+ signal sedclkout_i : std_logic;
+ signal mdccontrol_common_stat_reg_out : std_logic_vector(63 downto 0);
+
+ signal led_blink : std_logic;
+ signal blink_enable : std_logic;
+ signal time_counter : unsigned(9 downto 0);
begin
end if;
end if;
end process;
----------------------------------------------------------------------
--- Unused signals
----------------------------------------------------------------------
-reg_registers_in <= (others => '0');
---------------------------------------------------------------------
-- Optical Uplink
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
REGIO_HARDWARE_VERSION => x"23000001",
CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
DATA_BUFFER_DEPTH => 13,
CTRL_MPLEX => (others => '0'),
IOBUF_CTRL_GEN => (others => '0'),
STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => debug_lvl1_handler
);
---------------------------------------------------------------------
BUS_UNKNOWN_ADDR_IN(4) => '0',
--Debugging memory
BUS_READ_ENABLE_OUT(5) => readback_mem_read,
- BUS_WRITE_ENABLE_OUT(5) => readback_mem_write,
+ BUS_WRITE_ENABLE_OUT(5) => readback_mem_write_handler,
BUS_DATA_OUT(5*32+31 downto 5*32) => open,
BUS_ADDR_OUT(5*16+15 downto 5*16) => open,
BUS_TIMEOUT_OUT(5) => open,
BUS_DATAREADY_IN(5) => readback_mem_ready,
BUS_WRITE_ACK_IN(5) => '0',
BUS_NO_MORE_DATA_IN(5) => readback_mem_empty,
- BUS_UNKNOWN_ADDR_IN(5) => readback_mem_write,
+ BUS_UNKNOWN_ADDR_IN(5) => readback_mem_write_handler,
--Status Registers
BUS_READ_ENABLE_OUT(6) => statreg_read,
BUS_WRITE_ENABLE_OUT(6) => statreg_write,
end process;
+-------------------------------------------------------------------------------
+-- Readback FiFo (used for LVL1 trigger handler)
+-------------------------------------------------------------------------------
+ THE_TDC_READBACK_MEM : fifo_18x2k_oreg
+ port map (
+ Data(17 downto 0) => last_rb_fifo_input,
+ Clock => clk_100,
+ AmFullThresh => (others => '1'),
+ WrEn => readback_mem_write,
+ RdEn => readback_mem_read,
+ Reset => reset_internal,
+ Q => readback_mem_data_out(17 downto 0),
+ Empty => readback_mem_empty,
+ Full => readback_mem_full
+ );
+
+
+ rb_fifo_input(15 downto 0) <= debug_lvl1_handler;
+ rb_fifo_input(17 downto 16) <= "00";
+
+ process(clk_100)
+ begin
+ if rising_edge(clk_100) then
+ last_rb_fifo_input <= rb_fifo_input;
+ if rb_fifo_input /= last_rb_fifo_input and readback_mem_full = '0' then
+ readback_mem_write <= '1';
+ else
+ readback_mem_write <= '0';
+ end if;
+ last_rb_read_enable_in <= readback_mem_read;
+ readback_mem_ready <= last_rb_read_enable_in;
+ end if;
+ end process;
+ readback_mem_data_out(31 downto 18) <= (others => '0');
+
+
+
---------------------------------------------------------------------
-- Select Flash FF
---------------------------------------------------------------------
STAT_READ_ENABLE_IN => statreg_read,
STAT_READY_OUT => statreg_ready,
- RB_DATA_OUT => readback_mem_data_out,
- RB_READ_ENABLE_IN => readback_mem_read,
- RB_READY_OUT => readback_mem_ready,
- RB_EMPTY_OUT => readback_mem_empty,
+ RB_DATA_OUT => open, --readback_mem_data_out,
+ RB_READ_ENABLE_IN => '0', --readback_mem_read,
+ RB_READY_OUT => open, --readback_mem_ready,
+ RB_EMPTY_OUT => open, --readback_mem_empty,
- COMMON_STAT_REG_OUT => reg_common_stat_reg_in,
+ COMMON_STAT_REG_OUT => mdccontrol_common_stat_reg_out(63 downto 0),
COMMON_CTRL_REG_IN => reg_common_ctrl_reg_out,
+ STAT_REG_OUT => reg_registers_in,
CTRL_REG_IN => reg_registers_out,
DEBUG_OUT => debug_mdc_control_i
-------------------------------------------------------------------------------
-- LED
-------------------------------------------------------------------------------
- D(4) <= '1';
- D(3) <= '1';
- D(2) <= '1';
- D(1) <= '1';
+ D(4) <= not led_blink;
+ D(3) <= not led_blink;
+ D(2) <= not led_blink;
+ D(1) <= not led_blink;
+ process(clk_100)
+ begin
+ if rising_edge(clk_100) then
+ if timer_ticks(1) = '1' then
+ time_counter <= time_counter + to_unsigned(1,1);
+ end if;
+ if blink_enable = '1' then
+ led_blink <= time_counter(8);
+ else
+ led_blink <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ reg_common_stat_reg_in(13 downto 0) <= mdccontrol_common_stat_reg_out(13 downto 0);
+ reg_common_stat_reg_in(14) <= sederr_i;
+ reg_common_stat_reg_in(63 downto 15) <= mdccontrol_common_stat_reg_out(63 downto 15);
+ blink_enable <= reg_registers_out(32);
-------------------------------------------------------------------------------
-- pins not used
-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- SEU circuit
+-------------------------------------------------------------------------------
+-- CHECK_COMP: SEDAA
+-- -- synthesis translate_off
+-- generic map (
+-- OSC_DIV :string => "1"
+-- );
+-- -- synthesis translate_on
+-- port map (
+-- SEDENABLE => '1',--SED enable active high
+-- SEDSTART => '1',--SED start active high
+-- SEDFRCERR => '0',
+-- SEDERR => sederr_i, --pulse when s/th wrong
+-- SEDDONE => seddone_i,--open,--SED cycle complete active high
+-- SEDINPROG => sedinprog_i,--open,
+-- SEDCLKOUT => sedclkout_i--open
+-- );
+
+
end architecture;
trg_number_i <= (others => '0');
trg_type_i <= x"1";
trg_information_i<= (others => '0');
- wait for 4 ms;
+ wait for 1 ms;
COM_STOP_P <= '1';
wait for 100 ns;
COM_STOP_P <= '0';
jspc29 / mdcoep.git / commitdiff