all designs use Encoder_288

diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd
index bff8f06ed49b20a153de864d2736033aa5fcfaaa..db10ded64a35ecb0749fd8a37b24dd3561c29aab 100644 (file)
--- a/releases/tdc_v2.3/Channel_200.vhd
+++ b/releases/tdc_v2.3/Channel_200.vhd
@@ -168,6 +168,8 @@ architecture Channel_200 of Channel_200 is
   attribute syn_keep                : boolean;
   attribute syn_keep of ff_array_en : signal is true;
   attribute syn_keep of FSM_RD_STATE : signal is true;
+  attribute syn_keep of trg_win_end_tdc_flag : signal is true;
+  attribute syn_keep of trg_win_end_tdc : signal is true;
 
   attribute syn_hier : string;
   attribute syn_hier of Channel_200 : architecture is "firm";
@@ -354,20 +356,20 @@ begin  -- Channel_200
     end if;
   end process EpochCounterCapture;
 
-  --purpose: Encoder
-gen_Encoder304 : if FPGA_TYPE = 3 generate
-  Encoder : Encoder_304_Bit
-   port map (
-     RESET           => RESET_200,
-     CLK             => CLK_200,
-     START_IN        => encoder_start,
-     THERMOCODE_IN   => result,
-     FINISHED_OUT    => encoder_finished,
-     DECIMAL_CODE_OUT => encoder_data_out,
-     ENCODER_DEBUG   => encoder_debug);
-end generate;
-  --purpose: Encoder
-gen_Encoder288 : if FPGA_TYPE = 5 generate
+--   --purpose: Encoder
+-- gen_Encoder304 : if FPGA_TYPE = 3 generate
+--   Encoder : Encoder_304_Bit
+--    port map (
+--      RESET           => RESET_200,
+--      CLK             => CLK_200,
+--      START_IN        => encoder_start,
+--      THERMOCODE_IN   => result,
+--      FINISHED_OUT    => encoder_finished,
+--      DECIMAL_CODE_OUT => encoder_data_out,
+--      ENCODER_DEBUG   => encoder_debug);
+-- end generate;
+--   --purpose: Encoder
+-- gen_Encoder288 : if FPGA_TYPE = 5 generate
   Encoder : Encoder_288_Bit
     port map (
       RESET            => RESET_200,
@@ -381,7 +383,7 @@ gen_Encoder288 : if FPGA_TYPE = 5 generate
       CHAIN_VALID_OUT  => write_chain,
       CHAIN_DATA_OUT   => chain
       );
-end generate;
+-- end generate;
       
   RingBuffer_128_dyn : if RING_BUFFER_SIZE = 7 generate
     FIFO : FIFO_DC_36x128_DynThr_OutReg

diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd
index 9ffb423db28ac600d5538e9febfeddcf2b74b1d5..f2542321503d2960ee566ca3c483641a8b0c128a 100644 (file)
--- a/releases/tdc_v2.3/Encoder_288_Bit.vhd
+++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd
@@ -180,14 +180,25 @@ begin
     end if;
   end process Interval_Selection;
 
+gen_ROM_5 : if FPGA_TYPE = 5 generate  
 --  The_ROM : entity work.ROM_encoder_3 --SIMULATION
-  The_ROM : entity work.ROM_encoder_4   --REAL
+  The_ROM_5 : entity work.ROM_encoder_4   --REAL
     port map (
       Address    => address,
       OutClock   => CLK,
       OutClockEn => '1',
       Reset      => RESET,
       Q          => q_reg);
+end generate;
+gen_ROM_3 : if FPGA_TYPE = 3 generate  
+  The_ROM_3 : entity work.ROM_encoder_3   --REAL
+    port map (
+      Address    => address,
+      OutClock   => CLK,
+      OutClockEn => '1',
+      Reset      => RESET,
+      Q          => q_reg);
+end generate;
 
   address          <= start_pipeline(1) & interval_reg;
   interval_decimal <= q_reg(2 downto 0)                     when rising_edge(CLK);

diff --git a/releases/tdc_v2.3/LogicAnalyser.vhd b/releases/tdc_v2.3/LogicAnalyser.vhd
index 3c6091df7125270c8320fcddbb83ff695c8e5c59..854b4a5c4dd72105cd324711f892ef42c181bf2c 100644 (file)
--- a/releases/tdc_v2.3/LogicAnalyser.vhd
+++ b/releases/tdc_v2.3/LogicAnalyser.vhd
@@ -18,7 +18,8 @@ library work;
 
 entity LogicAnalyser is
   generic (
-    CHANNEL_NUMBER : integer range 2 to 64);
+    CHANNEL_NUMBER : integer range 2 to 64 := 2
+    );
 
   port (
     CLK        : in  std_logic;