LED ACT added

diff --git a/gbe_trb_ecp5/base/gbe_med_interface_single.vhd b/gbe_trb_ecp5/base/gbe_med_interface_single.vhd
index 22c579e17184aad20f005ba663e73544a99981e0..87c976c817257165968d998a7c1844baf31a9a44 100644 (file)
--- a/gbe_trb_ecp5/base/gbe_med_interface_single.vhd
+++ b/gbe_trb_ecp5/base/gbe_med_interface_single.vhd
@@ -224,6 +224,12 @@ architecture RTL of gbe_med_interface_single is
   signal delay_q                                  : std_logic_vector(7 downto 0);
   signal pulse                                    : std_logic;
 
+  signal led_timer                                : unsigned(19 downto 0);
+  signal led_timer_done_x                         : std_logic;
+  signal led_timer_done                           : std_logic;
+  signal led_activity_x                           : std_logic;
+  signal led_activity                             : std_logic_vector(1 downto 0);
+  
 begin
 
   -- We allow only one GbE in ECP5 for now
@@ -350,12 +356,12 @@ begin
   -- Status signals
   STATUS_OUT(7) <= '0';
   STATUS_OUT(6) <= '0';
-  STATUS_OUT(5) <= '0';
-  STATUS_OUT(4) <= pcs_rx_en;     -- SerDes RX activity
-  STATUS_OUT(3) <= pcs_tx_en;     -- SerDes TX activity
-  STATUS_OUT(2) <= an_complete;   -- GbE Autonegotiation completed
-  STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
-  STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
+  STATUS_OUT(5) <= led_activity(1); -- long LED signal for activity
+  STATUS_OUT(4) <= pcs_rx_en;       -- SerDes RX activity
+  STATUS_OUT(3) <= pcs_tx_en;       -- SerDes TX activity
+  STATUS_OUT(2) <= an_complete;     -- GbE Autonegotiation completed
+  STATUS_OUT(1) <= link_rx_ready;   -- SerDes Rx channel operational
+  STATUS_OUT(0) <= link_tx_ready;   -- SerDes TX channel operational
   
 --  -- "Good" debugging pins
 --  debug(7 downto 0)  <= sd_tx_data;
@@ -555,5 +561,29 @@ begin
   -- Debug
     DEBUG_OUT           => open
   );
-                
+
+  THE_LED_TIMER_PROC: process( CLK_125_IN )
+  begin
+    if( rising_edge(CLK_125_IN) ) then
+      led_timer_done <= led_timer_done_x;
+      led_timer      <= led_timer + 1;
+    end if;
+  end process THE_LED_TIMER_PROC;
+
+  led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
+  
+  led_activity_x <= pcs_rx_en or pcs_tx_en;
+  
+  THE_LED_ACT_PROC: process( CLK_125_IN )
+  begin
+    if( rising_edge(CLK_125_IN) ) then
+      if( led_activity_x = '1' ) then
+        led_activity(0) <= '1';
+      end if;
+      if( led_timer_done = '1' ) then
+        led_activity <= led_activity(0) & '0';
+      end if;
+    end if;
+  end process THE_LED_ACT_PROC;
+  
 end architecture RTL;

diff --git a/gbe_trb_ecp5/base/gbe_wrapper_single.vhd b/gbe_trb_ecp5/base/gbe_wrapper_single.vhd
index e065ab2d82a8ccba9775792fae2ba60d98c2c24c..d9752f8efd52f28b7f24ca38efa5e9fb25f6f7a2 100644 (file)
--- a/gbe_trb_ecp5/base/gbe_wrapper_single.vhd
+++ b/gbe_trb_ecp5/base/gbe_wrapper_single.vhd
@@ -220,7 +220,6 @@ architecture RTL of gbe_wrapper_single is
 begin
 
 --  assert hits if condition in brackets is true, or overall condition is false
---  assert not (dual_mode = 8)                           report "Note: DUAL with one slave port detected" severity note;
 
   assert not (NUMBER_OF_GBE_LINKS /= 1)                report "Error: only one GbE link allowed" severity error;
   assert not (LINKS_ACTIVE /= b"0001")                 report "Error: no / wrong GbE interface selected" severity error;