add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-#Media interface
+#Media interface (reset state machines)
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd"
-
-add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/rb_4k_9.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/fifo_4k_9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/sgl_ctrl.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd"
-
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test_random.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rng_trivium.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/gbe_med_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch0.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d0ch1_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch0.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes/serdes_d1ch1_softlogic.v"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v"
-# Choose your SerDes location here
-add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/d0ch0/serdes_gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/d0ch1/serdes_gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/d1ch0/serdes_gbe.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/d1ch1/serdes_gbe.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/fwd_test_random.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rng_trivium.vhd"
+
# Link Delay Measurement stuff
#add_file -vhdl -lib work "../../dlm/base/ddmtd.vhd"
#add_file -vhdl -lib work "../../dlm/base/deglitch.vhd"
signal dl_rx_frame_req : std_logic_vector(0 downto 0);
signal dl_rx_frame_ack : std_logic_vector(0 downto 0);
signal dl_rx_frame_avail : std_logic_vector(0 downto 0);
--- signal dl_tx_fifofull : std_logic_vector(0 downto 0);
-
+ signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX)
+ signal dl_tx_fifofull : std_logic_vector(0 downto 0);
+
-- 10: frame_start
-- 9 : fifo_wr
-- 8 : fifo_eof
-- 7..0: data
signal ul_rx_data : std_logic_vector(10 downto 0);
signal ul_tx_data : std_logic_vector(10 downto 0);
- signal ul_tx_data_q : std_logic_vector(10 downto 0);
signal ul_tx_fifofull : std_logic;
signal ul_rx_frame_avail : std_logic;
signal ul_rx_frame_req : std_logic;
signal ul_rx_frame_ack : std_logic;
signal ul_rx_fifofull : std_logic;
+
+ -- 10: frame_start
+ -- 9 : fifo_wr
+ -- 8 : fifo_eof
+ -- 7..0: data
+ signal local_rx_data : std_logic_vector(10 downto 0); -- CPU (RX) to 1:2 MUXes
+ signal local_rx_frame_avail : std_logic;
+ signal local_rx_frame_req : std_logic;
+ signal local_rx_frame_ack : std_logic;
+ signal local_rx_fifofull : std_logic;
+ signal local_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to CPU (TX)
+ signal local_tx_fifofull : std_logic;
+ -- these signals go from multiplexer to UL (TX)
- signal port_sel : std_logic_vector(0 downto 0);
+ signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes
+
+ signal dl_rx_port_sel : std_logic_vector(0 downto 0);
+ signal ul_tx_port_sel : std_logic;
+ signal dl_tx_port_sel : std_logic;
+ signal local_tx_port_sel : std_logic;
signal sniffer_data : std_logic_vector(7 downto 0);
signal sniffer_wr : std_logic;
signal sniffer_eof : std_logic;
signal sniffer_error : std_logic;
-
signal fwd_mac_int : std_logic_vector(47 downto 0);
signal fwd_ip_int : std_logic_vector(31 downto 0);
signal fwd_port_int : std_logic_vector(15 downto 0);
signal tick_us_int : std_logic;
signal reboot_int : std_logic;
+
+ signal sgl_debug : std_logic_vector(15 downto 0);
begin
---------------------------------------------------------------------------
-- GbE interface
---------------------------------------------------------------------------
- GBE_MED_INTERFACE: entity gbe_med_fifo_single
+ GBE_MED_INTERFACE: entity gbe_med_fifo
+ generic map(
+ SERDES_NUM => 0
+ )
port map(
RESET => reset_i,
RESET_N => reset_n_i,
CLEAR_N => clear_n_i,
CLK_125 => clk_sys,
-- FIFO interface RX
- FIFO_FULL_IN => ul_rx_fifofull,
+ FIFO_FULL_IN => '0', -- BUG ul_rx_fifofull,
FIFO_WR_OUT => ul_rx_data(9),
FIFO_DATA_OUT => ul_rx_data(8 downto 0),
FRAME_START_OUT => ul_rx_data(10),
FRAME_ACK_OUT => ul_rx_frame_ack,
FRAME_AVAIL_OUT => ul_rx_frame_avail,
-- FIFO interface TX
- FIFO_WR_IN => ul_tx_data_q(9),
- FIFO_DATA_IN => ul_tx_data_q(8 downto 0),
- FRAME_START_IN => ul_tx_data_q(10),
+ FIFO_WR_IN => ul_tx_data(9),
+ FIFO_DATA_IN => ul_tx_data(8 downto 0),
+ FRAME_START_IN => ul_tx_data(10),
FIFO_FULL_OUT => ul_tx_fifofull,
--SFP Connection
SD_PRSNT_N_IN => SFP_MOD_0,
-- debug(33..20) are on GPIO
-- 33 = CLK2 (white/green)
-- 32 = CLK1 (white/blue)
---
--- debug(7 downto 0) <= ul_rx_data(7 downto 0);
--- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
--- debug(16) <= ul_rx_data(9);
--- debug(17) <= ul_tx_data_q(9);
--- debug(18) <= ul_rx_data(10);
--- debug(19) <= ul_tx_data_q(10);
--- debug(20) <= ul_rx_data(8);
--- debug(21) <= ul_tx_data_q(8);
--- debug(22) <= ul_rx_frame_req;
--- debug(23) <= ul_rx_frame_ack;
--- debug(24) <= ul_rx_frame_avail;
--- debug(25) <= dl_rx_frame_req(0);
--- debug(26) <= dl_rx_frame_ack(0);
--- debug(27) <= dl_rx_frame_avail(0);
--- debug(28) <= port_sel(0);
--- debug(29) <= ul_rx_fifofull;
--- debug(30) <= ul_tx_fifofull;
--- debug(31) <= '0';
--- debug(32) <= tick_int;
--- debug(33) <= clk_sys;
+
+ debug(0) <= ul_rx_frame_avail;
+ debug(1) <= ul_rx_frame_req;
+ debug(2) <= ul_rx_frame_ack;
+ debug(3) <= ul_tx_fifofull;
+ debug(4) <= dl_rx_frame_avail(0);
+ debug(5) <= dl_rx_frame_req(0);
+ debug(6) <= dl_rx_frame_ack(0);
+ debug(7) <= ul_rx_data(9);
+ debug(8) <= ul_rx_data(10);
+ debug(9) <= ul_tx_data(9);
+ debug(10) <= ul_tx_data(10);
+ debug(11) <= dl_rx_port_sel(0);
+ debug(12) <= dl_tx_port_sel;
+ debug(13) <= local_tx_port_sel;
+ debug(14) <= ul_tx_port_sel;
+ debug(15) <= '0';
+ debug(19 downto 16) <= sgl_debug(3 downto 0);
+ debug(20) <= '0';
+ debug(21) <= '0';
+ debug(22) <= '0';
+ debug(23) <= '0';
+ debug(24) <= '0';
+ debug(25) <= '0';
+ debug(26) <= '0';
+ debug(27) <= '0';
+ debug(28) <= '0';
+ debug(29) <= '0';
+ debug(30) <= '0';
+ debug(31) <= '0';
+ debug(32) <= '0';
+ debug(33) <= clk_sys;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
- -- scattering: data from uplink is distributed to downlinks
- THE_SCATTER: entity scatter_ports
- port map(
- CLK => clk_sys,
- RESET => reset_i,
- --
--- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0), -- not needed, only SCTRL at the moment
- FIFO_FULL_OUT => ul_rx_fifofull,
- FRAME_AVAIL_IN => ul_rx_frame_avail,
- FRAME_REQ_OUT => ul_rx_frame_req,
- FRAME_ACK_IN => ul_rx_frame_ack,
- CYCLE_DONE_OUT => open,
- --
- DEBUG => open
- );
-
- THE_GATHER: entity gather_ports
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+ THE_SGL_CTRL: entity sgl_ctrl
port map(
- CLK => clk_sys,
- RESET => reset_i,
- --
- FRAME_AVAIL_IN(0 downto 0) => dl_rx_frame_avail(0 downto 0),
- FRAME_REQ_OUT(0 downto 0) => dl_rx_frame_req(0 downto 0),
- FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack(0 downto 0),
- PORT_SELECT_OUT(0 downto 0) => port_sel,
- PORT_MUX_OUT => open,
- CYCLE_DONE_OUT => open,
+ CLK => clk_sys,
+ RESET => reset_i,
+ -- UL port
+ UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full
+ UL_FRAME_AVAIL_IN => ul_rx_frame_avail, -- UL RX has frames for DL/LOCAL
+ UL_FRAME_REQ_OUT => ul_rx_frame_req, -- UL RX request to send
+ UL_FRAME_ACK_IN => ul_rx_frame_ack, -- UL RX sent acknowledge
+ -- DL ports (includes SCTRL)
+ DL_FIFOFULL_IN(0 downto 0) => dl_tx_fifofull, -- DL TXn FIFO is full
+ DL_FRAME_AVAIL_IN(0 downto 0) => dl_rx_frame_avail, -- DL RXn has frames for UL/LOCAL
+ DL_FRAME_REQ_OUT(0 downto 0) => dl_rx_frame_req, -- DL RXn request to send
+ DL_FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge
+ -- CPU port -- not needed
+ -- MUX control
+ DL_RX_PORT_SEL_OUT(0 downto 0) => dl_rx_port_sel,
+ DL_RX_PORT_MUX_OUT => open,
+ DL_TX_PORT_SEL_OUT => dl_tx_port_sel,
+ LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel,
+ UL_TX_PORT_SEL_OUT => ul_tx_port_sel,
--
- DEBUG => open
+ DEBUG => sgl_debug --open
);
- THE_QUICK_MUX: process( port_sel, dl_rx_data )
+ local_rx_data <= (others => '0'); -- no local CPU port
+
+ THE_DL_RX_MUX: process( dl_rx_port_sel, dl_rx_data )
begin
- case port_sel is
- when b"1" => ul_tx_data <= dl_rx_data(0);
- when others => ul_tx_data <= (others => '0');
+ case dl_rx_port_sel is
+ when b"1" => switch_rx_data <= dl_rx_data(0);
+ when others => switch_rx_data <= (others => '0');
end case;
- end process THE_QUICK_MUX;
+ end process THE_DL_RX_MUX;
+
+ ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data; -- not needed
- ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
+ local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data; -- not needed
+
+ dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; -- not needed
+
+-- -- scattering: data from uplink is distributed to downlinks
+-- THE_SCATTER: entity scatter_ports
+-- port map(
+-- CLK => clk_sys,
+-- RESET => reset_i,
+-- --
+---- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0), -- not needed, only SCTRL at the moment
+-- FIFO_FULL_OUT => ul_rx_fifofull,
+-- FRAME_AVAIL_IN => ul_rx_frame_avail,
+-- FRAME_REQ_OUT => ul_rx_frame_req,
+-- FRAME_ACK_IN => ul_rx_frame_ack,
+-- CYCLE_DONE_OUT => open,
+-- --
+-- DEBUG => open
+-- );
+--
+-- THE_GATHER: entity gather_ports
+-- port map(
+-- CLK => clk_sys,
+-- RESET => reset_i,
+-- --
+-- FRAME_AVAIL_IN(0 downto 0) => dl_rx_frame_avail(0 downto 0),
+-- FRAME_REQ_OUT(0 downto 0) => dl_rx_frame_req(0 downto 0),
+-- FRAME_ACK_IN(0 downto 0) => dl_rx_frame_ack(0 downto 0),
+-- PORT_SELECT_OUT(0 downto 0) => port_sel,
+-- PORT_MUX_OUT => open,
+-- CYCLE_DONE_OUT => open,
+-- --
+-- DEBUG => open
+-- );
+--
+-- THE_QUICK_MUX: process( port_sel, dl_rx_data )
+-- begin
+-- case port_sel is
+-- when b"1" => ul_tx_data <= dl_rx_data(0);
+-- when others => ul_tx_data <= (others => '0');
+-- end case;
+-- end process THE_QUICK_MUX;
+--
+-- ul_tx_data_q <= ul_tx_data when rising_edge(clk_sys);
---------------------------------------------------------------------------
-- GbE wrapper without med interface
RESET => reset_i,
GSR_N => reset_n_i,
-- we connect to FIFO interface directly
- -- FIFO interface TX (transmit frames)
+ -- FIFO interface TX (send frames)
FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
FIFO_FULL_IN => ul_tx_fifofull,
FIFO_WR_OUT => dl_rx_data(0)(9),
MAKE_RESET_OUT => reset_via_gbe,
-- debug
STATUS_OUT => status(15 downto 8),
- DEBUG_OUT => debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
+ DEBUG_OUT => open --debug(95 downto 64) --(17 downto 0 ==> 81 downto 64)
);
THE_FWD_TEST: entity fwd_test_random
DEBUG => open
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--- debug(19..0) are on INTCOM
--- debug(33..20) are on GPIO
--- 33 = CLK2 (white/green)
--- 32 = CLK1 (white/blue)
-
- debug(7 downto 0) <= fwd_data_int;
- debug(8) <= fwd_ready_int;
- debug(9) <= fwd_full_int;
- debug(10) <= fwd_sop_int;
- debug(11) <= fwd_eop_int;
- debug(12) <= fwd_data_valid_int;
- debug(13) <= fwd_busy_int;
- debug(14) <= additional_reg(31);
- debug(15) <= tick_us_int;
- debug(16) <= debug(64);
- debug(17) <= debug(65);
- debug(18) <= debug(66);
- debug(19) <= debug(68);
- debug(20) <= debug(69);
- debug(21) <= debug(70);
- debug(22) <= debug(71);
- debug(23) <= debug(72);
- debug(24) <= debug(73);
- debug(25) <= debug(74);
- debug(26) <= debug(75);
- debug(27) <= debug(76);
- debug(28) <= debug(77);
- debug(29) <= debug(78);
- debug(30) <= debug(79);
- debug(31) <= debug(80);
- debug(32) <= debug(81);
- debug(33) <= clk_sys;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-
---------------------------------------------------------------------------
-- SCTRL endpoint for GbE standalone
---------------------------------------------------------------------------
I2C_SDA => I2C_SDA,
-- Generic stuff
TIMERS_OUT => timer,
- MY_ADDRESS_OUT => open -- BUG?
+ MY_ADDRESS_OUT => open
);
common_stat_reg <= (others => '0');
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
LED(3) <= not additional_reg(7); --'0';
- LED(2) <= not additional_reg(6); --'0';
+ LED(2) <= not '1'; --additional_reg(6); --'0';
LED(1) <= not additional_reg(5); --'0';
LED(0) <= not additional_reg(4); --'0';
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- debug(19..0) are on INTCOM
+-- debug(33..20) are on GPIO
+-- 33 = CLK2 (white/green)
+-- 32 = CLK1 (white/blue)
+--
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data_q(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data_q(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data_q(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data_q(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(28) <= port_sel(0);
+-- debug(29) <= ul_rx_fifofull;
+-- debug(30) <= ul_tx_fifofull;
+-- debug(31) <= '0';
+-- debug(32) <= tick_int;
+-- debug(33) <= clk_sys;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
end architecture;