attribute INITVAL_17 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute INITVAL_16 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute INITVAL_15 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_14 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_13 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_12 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_11 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_10 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_0A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_09 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
--- attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
- attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018";
- attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11
-
- -- attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400000000340000000030000000001C0000000018";
- -- attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00000000140000000010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11
+-------------------------------------------------------------------------------
+-- calibration
+-------------------------------------------------------------------------------
+ attribute INITVAL_14 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
+ attribute INITVAL_13 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4";
+ attribute INITVAL_12 of initialization_RAM_0_0_0 : label is "0x0009900084000990006400099000440009900024000BD00184000BD00164000BD00144000BD00124";
+ attribute INITVAL_11 of initialization_RAM_0_0_0 : label is "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024";
+ attribute INITVAL_10 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
+ attribute INITVAL_0F of initialization_RAM_0_0_0 : label is "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024";
+ attribute INITVAL_0E of initialization_RAM_0_0_0 : label is "0X000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024";
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+ attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018";
+ attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11
- attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC";--REGISTER_3
- --<REGISTER_3
- attribute INITVAL_0A of initialization_RAM_0_0_0 : label is "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128";
- attribute INITVAL_09 of initialization_RAM_0_0_0 : label is "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028";--REGISTER_2
- attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4";--REGISTER_1
+ attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC";--REGISTER_3
+ --<REGISTER_3
+ attribute INITVAL_0A of initialization_RAM_0_0_0 : label is "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128";
+ attribute INITVAL_09 of initialization_RAM_0_0_0 : label is "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028";--REGISTER_2
+ attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4";--REGISTER_1
--<REGISTER_1
- attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120";
- attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0 --
+ attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120";
+ attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0
attribute INITVAL_05 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
attribute INITVAL_04 of initialization_RAM_0_0_0 : label is "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 1D 19 15 11
- --attribute INITVAL_05 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
- --attribute INITVAL_04 of initialization_RAM_0_0_0 : label is "0x000610001C000610001800061000140006100010000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 1D 19 15 11
attribute INITVAL_03 of initialization_RAM_0_0_0 : label is "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C";--REGISTER_3
attribute INITVAL_02 of initialization_RAM_0_0_0 : label is "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028";--REGISTER_2
attribute INITVAL_01 of initialization_RAM_0_0_0 : label is "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024";--REGISTER_1
INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+
+
-------------------------------------------------------------------------------
--- 1 LONG MB
+-- FEE CALIBRATION (1 LONG): START REGISTER 1
-------------------------------------------------------------------------------
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
+ INITVAL_13=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",
+ INITVAL_12=> "0x0009900084000990006400099000440009900024000BD00184000BD00164000BD00144000BD00124",
+ --> CHANGE THE MODE
+ INITVAL_11=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1
+
+-------------------------------------------------------------------------------
+-- FEE CALIBRATION (1 SHORT):
+-------------------------------------------------------------------------------
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
+
+ INITVAL_0F=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1
+--> CHANGE THE MODE
+ INITVAL_0E=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1
+
+-------------------------------------------------------------------------------
+-- FEE INIT:1 LONG MB
+-------------------------------------------------------------------------------
+
INITVAL_0D=> "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018",
INITVAL_0C=> "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11
-- INITVAL_0D=> "0x000000000000000000000000000000000100011400000000340000000030000000001C0000000018",
INITVAL_08=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",--REGISTER_1
--<REGISTER_1
INITVAL_07=> "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120",
- INITVAL_06=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0
+ INITVAL_06=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0
+ --
------------------------------------------------------------------------------
-- 1 SHORT MB
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- SIGNALS for RAM
-------------------------------------------------------------------------------
- RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_ADDRESS_IN : in std_logic_vector(8 downto 0);
RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
RAM_READ_ENABLE_IN : in std_logic;
signal up_counter_i, up_counter_register_2 : std_logic;
signal time_counter : std_logic_vector(width - 1 downto 0);
signal calibration_counter_0 : std_logic_vector (width - 1 downto 0);
- signal calibration_counter_1 : std_logic_vector (width - 1 downto 0);
- signal clear_calibration_counter_0, clear_calibration_counter_1 : std_logic;
+-- signal calibration_counter_1 : std_logic_vector (width - 1 downto 0);
+ signal clear_calibration_counter_0 : std_logic;
+-- signal clear_calibration_counter_1 : std_logic;
signal reg_A_DST, next_A_DST : std_logic;
signal reg_A_AOD, next_A_AOD : std_logic;
signal counter_delay : std_logic_vector(7 downto 0);
signal control_register_0, control_register_0_temp, up_control_register_0 : std_logic;
signal cpld_register_data : std_logic_vector(8 downto 0);
- signal external_ram_address : std_logic_vector(9 downto 0);
+ signal external_ram_address : std_logic_vector(8 downto 0);
signal external_ram_data : std_logic_vector(15 downto 0);
signal external_read_enable, external_write_enable, write_or_read_enable : std_logic;
signal clear_time_counter : std_logic;
-- );
-- -- End of RAMB16_S9_S9 instantiation
--- external_ram_address <= RAM_ADDRESS_IN;
--- external_ram_data <= RAM_DATA_IN;
+ external_ram_address <= RAM_ADDRESS_IN;
+ external_ram_data <= RAM_DATA_IN;
-- external_read_enable <= RAM_READ_ENABLE_IN;
--- external_write_enable <= RAM_WRITE_ENABLE_IN;
+ external_write_enable <= RAM_WRITE_ENABLE_IN;
-- write_or_read_enable <= external_read_enable or external_write_enable;
RAM_configuration: initialization_RAM
port map (
DataInA => (others => '0'),--DataInA_i,
- DataInB => (others => '0'),--DataInB_i,
+ DataInB => external_ram_data,--DataInB_i,
AddressA => counter_ram(8 downto 0), --AddressA_i, --9 bits
- AddressB => (others => '0'),--AddressB_i,
+ AddressB => external_ram_address,--(others => '0'),--AddressB_i,
ClockA => CLK,--ClockA_i,
- ClockB => '0',--CLK,--ClockB_i,
+ ClockB => CLK,--ClockB_i,
ClockEnA => '1',--ClockEnA_i,
- ClockEnB => '0',--ClockEnB_i,
- WrA => '0',--WrA_i,
- WrB => '0',--WrB_i,
+ ClockEnB => '1',--'0',--ClockEnB_i,
+ WrA => '0',
+ WrB => external_write_enable,
ResetA => '0',--ResetA_i,
ResetB => '0',--ResetB_i,
QA => send_data, -- RAM_DATA_OUT, -- Port A 16-bit Data Output
- QB => open-- Port B 16-bit Data Output
+ QB => RAM_DATA_OUT --open-- Port B 16-bit Data Output
);
-------------------------------------------------------------------------------
--purpose: state machine synchronization
calibration_stop_counter_ram,
time_counter, CALIBRATION_STEP_TDC_SETUP,
CALIBRATION_TRIGGER_TDC_SETUP, calibration_counter_0,
- calibration_counter_1, counter_register_1, counter_delay,
+ counter_register_1, counter_delay,
bus_chain, control_register_0,
cpld_register_data)
begin
next_TDC_SETTING_LOADED_OUT <= '0';
A_ADD(8 downto 0) <= (others => '0');
clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
up_control_register_0 <= '0';
clear_time_counter <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
clear_time_counter <= '1';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
--- if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
--- next_state <= calibration_state_0;--bus_chain <= x"1" 1 short MB in the bus
--- else
--- next_state <= stop_state;
--- end if;
- next_state <= stop_state;
--------------------------------------------------------------------------------
--- STOP ROC DATA
--------------------------------------------------------------------------------
+ if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
+ next_state <= calibration_state_0;--bus_chain <= x"1" 1 short MB in the bus
+ else
+ next_state <= stop_state;
+ end if;
+
-------------------------------------------------------------------------------
-- CALIBRATION PROCESS, Here I use different states, I could use the same I
-- previously used but It easier in case the timing signal is different for
next_A_DST <= '0';
next_A_AOD <= '0';
up_counter_i <= '0';
- A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15"; --here always the same I do not use
- --the ram
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
+ A_ADD(8 downto 0) <= cpld_register_data;
+--'1' & x"15"; --here always the same I do not use
+--the ram
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_state_1;
else
next_state <= calibration_state_0;
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15";
- clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '0';
- if calibration_counter_1 >= time_limit then
+ if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_state_2;
else
next_state <= calibration_state_1;
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15";
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_state_3;
else
next_state <= calibration_state_2;
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= x"00" & '0';
- clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '0';
- if calibration_counter_1 >= time_limit then
+ if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_state_4;
else
next_state <= calibration_state_3;
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= x"00" & '0';
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_state_5;
else
next_state <= calibration_state_4;
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= x"00" & '0';
- clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '0';
- if calibration_counter_1 >= time_limit then
- -- next_state <= wait_calibration_state_6;
+ if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= test_wait;
else
next_state <= calibration_state_5;
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= x"00" & '0';
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
--- if counter_delay >= "01111111" then
--- next_state <= wait_calibration_state_6;
--- else
--- next_state <= test_wait;
--- end if;
+ clear_calibration_counter_0 <= '1';
if control_register_0 = '0' then
next_state <= test_wait_1;
elsif control_register_0 = '1' then
up_counter_i <= '0';
A_ADD(8 downto 0) <= x"00" & '0';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
up_control_register_0 <= '1';
- if (bus_chain = x"2" or bus_chain = x"4") then --2 short or 2 long in chain
- next_state <= calibration_state_0; --repeat and write again
- else
+-- if (bus_chain = x"2" or bus_chain = x"4") then --2 short or 2 long in chain
+-- next_state <= calibration_state_0; --repeat and write again
+-- else
next_state <= wait_calibration_state_6;
- end if;
+-- end if;
------------------------------------------------------------------------------
--
------------------------------------------------------------------------------
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
+ clear_calibration_counter_0 <= '1';
if CALIBRATION_STEP_TDC_SETUP = x"1" then
next_state <= dummy_calibration_state;
else
next_A_AOD <= '0';
up_counter_i <= '1';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
+ clear_calibration_counter_0 <= '1';
next_state <= dummy_calibration_state_2;
when dummy_calibration_state_2 => --start loading data
next_A_AOD <= '0';
up_counter_i <= '1';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_address_no_strobe_0;
-------------------------------------------------------------------------------
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_address_with_strobe_0;
else
next_state <= calibration_address_no_strobe_0;
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '0';
- if calibration_counter_1 >= time_limit then
+ if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_address_no_strobe_1;
else
next_state <= calibration_address_with_strobe_0;
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(8 downto 0);
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_dummy_wait;
else
next_state <= calibration_address_no_strobe_1;
up_counter_i <= '1';
A_ADD(8 downto 0) <= send_data(8 downto 0);
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
next_state <= calibration_data_no_strobe_0;
---------------------------------------------------------------------------
--CALIBRATION: WRITE DATA PART
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';--x"17"; --send_data;. .
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_data_with_strobe_0;
else
next_state <= calibration_data_no_strobe_0;
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
- clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '0';
- if calibration_counter_1 >= time_limit then
+ if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_data_no_strobe_1;
else
next_state <= calibration_data_with_strobe_0;
next_A_AOD <= '1';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '1';
if calibration_counter_0 >= time_limit then
+ clear_calibration_counter_0 <= '1';
next_state <= calibration_data_no_strobe_2;
else
next_state <= calibration_data_no_strobe_1;
up_counter_i <= '1';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
next_state <= calibration_maximum_counter_value;
when calibration_maximum_counter_value =>
next_A_AOD <= '0';
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
- clear_calibration_counter_0 <= '0';
- clear_calibration_counter_1 <= '0';
if counter_ram >= calibration_stop_counter_ram then
+ clear_calibration_counter_0 <= '1';
next_state <= wait_mode_load;
else
next_state <= calibration_address_no_strobe_0; --goes again to load next address
end if;
--counter_register_1 = x"0" means REGISTER 1 has been loaded the first time
---counter_register_1 = x"1" means REGISTER 1 has been loaded the twice and I
+--counter_register_1 = x"1" means REGISTER 1 has been loaded twice and I
--finished the calibration process.
when wait_mode_load => --08 08 48
next_debug_register <= x"1D";
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
if (CALIBRATION_STEP_TDC_SETUP = x"3" and counter_register_1 = x"0") then
next_state <= dummy_calibration_state_3;
- elsif CALIBRATION_STEP_TDC_SETUP = x"3" and counter_register_1 = x"1" then
+ elsif (CALIBRATION_STEP_TDC_SETUP = x"3" and counter_register_1 = x"1") then
next_state <= calibration_finished;
else
next_state <= wait_mode_load;
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
up_counter_register_2 <= '1'; --use second part of CAL1
next_state <= calibration_address_no_strobe_0;
- -- next_state <= dummy_calibration_state_3;
- -- next_debug_register <= x"1E";
-
+
when calibration_finished => --go to stop state and wait the next
--calibration trigger
next_debug_register <= x"1E";
up_counter_i <= '0';
A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
clear_calibration_counter_0 <= '1';
- clear_calibration_counter_1 <= '1';
if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
next_state <= calibration_state_0;
else
current_state = calibration_maximum_counter_value or
current_state = wait_mode_load or
current_state = calibration_finished or
+
current_state = calibration_state_0 or
current_state = calibration_state_1 or
current_state = calibration_state_2 or
calibration_offset_ram <= (others => '0');
stop_counter_ram <= (others => '0');
offset_ram <= (others => '0');
+
-------------------------------------------------------------------------------
--CALIBRATION
-------------------------------------------------------------------------------
--- elsif process_trigger_type = x"C" then
--- if bus_chain = x"1" then --1 short MB is configured
--- calibration_stop_counter_ram_0 <= "1010011111";-- "1010110001";
--- calibration_offset_ram <= "1010001110";
--- calibration_stop_counter_ram_1 <= "1010110001";--"1011100000";
--- elsif bus_chain = x"2" then --2 short MBs are configured in the same bus
--- calibration_stop_counter_ram_0 <= "1011011111";--0x2DF
--- calibration_offset_ram <= "1010111110";--0x2BE
--- calibration_stop_counter_ram_1 <= "1100000011";--0x303
--- -------------------------------------------------------------------------------
--- --
--- -------------------------------------------------------------------------------
--- elsif bus_chain = x"3" then --1 long MB is configured
--- calibration_stop_counter_ram_0 <= "1100100111";--0x327
--- calibration_offset_ram <= "1100001110";--0x30E
--- calibration_stop_counter_ram_1 <= "1101000001"; --0x341
-
--- elsif bus_chain = x"4" then --2 long MBs are configured in the same bus
--- calibration_stop_counter_ram_0 <= "1101111111"; --x37F
--- calibration_offset_ram <= "1101001110"; --0x34E
--- calibration_stop_counter_ram_1 <= "1110110011"; --0x3B3
--- end if;
+ elsif process_trigger_type = x"C" then
+ if bus_chain = x"1" then --1 short MB is configured
+ calibration_stop_counter_ram_0 <= "00" & x"EF";-- stop wrting the first register,
+ -- before change the mode line
+
+ calibration_offset_ram <= "00" & x"DE";--x"E0";
+ calibration_stop_counter_ram_1 <= "01" & x"01"; --finish calibration 101
+
+-- elsif bus_chain = x"2" then --1 long MB is configured
+-- calibration_stop_counter_ram_0 <= "1011011111";--0x2DF
+-- calibration_offset_ram <= "1010111110";--0x2BE
+-- calibration_stop_counter_ram_1 <= "1100000011";--0x303
+ end if;
+
-------------------------------------------------------------------------------
--BEGRUN TRIGGER
-------------------------------------------------------------------------------
elsif process_trigger_type = x"B" then
- if bus_chain = x"1" then --1 short MB is configured
+ if bus_chain = x"1" then --1 short MB is configured
stop_counter_ram <= "00" & x"51"; --"0100000001"; --x"101"
offset_ram <= "00" & x"00";
- elsif bus_chain = x"2" then --1 long MB is configured
- stop_counter_ram <= "00" & x"DA";--"0110001001"; --x"189"
- offset_ram <= "00" & x"60";--"0100010000"; --x"110"
+-- elsif bus_chain = x"2" then --1 long MB is configured
+-- stop_counter_ram <= "00" & x"DA";--"0110001001"; --x"189"
+-- offset_ram <= "00" & x"60";--"0100010000"; --x"110"
end if;
end if;
end if;
process (CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1' or
- current_state = stop_state or
- current_state = calibration_finished)
- then
+ if (RESET = '1' or current_state = stop_state or
+ current_state = calibration_finished) then
temp_counter_ram <= (others => '0');
elsif up_counter_i = '1' then
temp_counter_ram <= temp_counter_ram + 1;
end if;
end if;
end process;
---counter_ram <= temp_counter_ram;
-counter_ram <= temp_counter_ram + offset_ram;
+--counter_ram <= temp_counter_ram + offset_ram;
+counter_ram <= (temp_counter_ram + offset_ram) when process_trigger_type <= x"B" else (temp_counter_ram + calibration_offset_ram);
---counter_ram <= (temp_counter_ram + offset_ram) when process_trigger_type <= x"B"
--- else (temp_counter_ram + calibration_offset_ram);
--------------------------------------------------------------------------------
--- OFFSET COUNTER RAM
--------------------------------------------------------------------------------
--- process (CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- counter_ram <= (others => '0');
--- elsif (process_trigger_type = x"B") then
--- counter_ram <= temp_counter_ram + offset_ram; --!ok per calibration (temp_counter_ram + "0010110000");
--- else
--- counter_ram <= temp_counter_ram + offset_ram; --!ok epr cal(temp_counter_ram + "1010001110");
--- end if;
--- end if;
--- end process;
-------------------------------------------------------------------------------
--counter to check when I reach half CAL file.
--counter_register_2 = "0" I'm writing the FIRST part
-------------------------------------------------------------------------------
calibration_stop_counter_ram <= (calibration_stop_counter_ram_0) when counter_register_2 = x"0"
else (calibration_stop_counter_ram_1);
--- process (CLK)
--- begin
--- if rising_edge(CLK) then
--- if (RESET = '1' or current_state = calibration_finished) then
--- calibration_stop_counter_ram <= (others => '0');
--- elsif counter_register_2 = x"0" then
--- calibration_stop_counter_ram <= "1010011111"; --"1010100000";
--- else
--- calibration_stop_counter_ram <= "1010110001";
--- end if;
--- end if;
--- end process;
+
-------------------------------------------------------------------------------
-- CALIBRATION COUNTERs. I use these to keep the state on for a certain time
-------------------------------------------------------------------------------
if RESET = '1' or clear_calibration_counter_0 = '1' then
calibration_counter_0 <= (others => '0');
elsif (current_state = calibration_state_0 or
+ current_state = calibration_state_1 or
current_state = calibration_state_2 or
+ current_state = calibration_state_3 or
current_state = calibration_state_4 or
+ current_state = calibration_state_5 or
+
current_state = calibration_address_no_strobe_0 or
+ current_state = calibration_address_with_strobe_0 or
current_state = calibration_address_no_strobe_1 or
current_state = calibration_data_no_strobe_0 or
+ current_state = calibration_data_with_strobe_0 or
current_state = calibration_data_no_strobe_1 or
- current_state = wait_calibration_state_6)
- then
+ current_state = calibration_data_no_strobe_2)
+ then
calibration_counter_0 <= calibration_counter_0 + 1;
end if;
end if;
end process;
-process (CLK)
-begin -- process
- if rising_edge(CLK) then
- if RESET = '1' or clear_calibration_counter_1 = '1' then
- calibration_counter_1 <= (others => '0');
- elsif (current_state = calibration_state_1 or
- current_state = calibration_state_3 or
- current_state = calibration_state_5 or
- current_state = calibration_address_with_strobe_0 or
- current_state = calibration_data_with_strobe_0)
- then
- calibration_counter_1 <= calibration_counter_1 + 1;
- end if;
- end if;
-end process;
-
process (CLK)
begin -- process
if rising_edge(CLK) then
end process;
control_register_0 <= control_register_0_temp;
-cpld_register_data <= '1' & x"15" when control_register_0 = '0' else ('1' & x"16");
+--OLD VERSION
+--cpld_register_data <= '1' & x"15" when control_register_0 = '0' else ('1' & x"16");
+--OEPB
+cpld_register_data <= '1' & x"14" when control_register_0 = '0' else ('1' & x"16");
end behaviour;
jspc29 / mdcoep.git / commitdiff