\item Register 0xd412 contains the read-back of data from SPI. Content depends on slave chip.
\end{itemize*}
+\paragraph*{VHDL Configuration}
+The number of bits per word can be set with a generic in the VHDL component instantiation. If a value below 32 is chosen, the upper bits in all registers are ignored.
+The number of waitcycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz.
+
\paragraph*{Configuration File}
The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
The ASCII format is shown below, the commands can be found in table~\ref{ltc2600cmd}.