trigger generation: option to use edge detect before stretcher

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 52a0a7dd3f9ff9e1909e57e5b0f00a1960a9a327..05f86f1eea088d9051468dbce0ae943bd4358413 100644 (file)
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -44,11 +44,12 @@ signal inp_edge     : std_logic_vector(INPUTS-1 downto 0) := (others => '0');
 signal output_i     : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal out_reg      : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal got_any_stretch : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
-signal got_any_edge : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
+signal got_any_edge    : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal got_coincidence : std_logic;
 signal got_simplecoin  : std_logic;
-signal coin_enable  : std_logic  := '0';
-signal set_stretcher                                : unsigned(5 downto 0);
+signal coin_enable     : std_logic  := '0';
+signal set_stretcher   : unsigned(5 downto 0);
+signal set_stretchedge : std_logic;
 
 type unsigned7_arr is array(0 to 2) of unsigned(7 downto 0);
 signal current_multiplicity0, current_multiplicity1 : unsigned7_arr;
@@ -138,6 +139,7 @@ begin
       multiplicity_enable(0)(63 downto 32) <= BUS_RX.data;
     elsif BUS_RX.addr(6 downto 0) = "0110110" then
       set_stretcher <= unsigned(BUS_RX.data(5 downto 0));
+      set_stretchedge <= BUS_RX.data(8);
     elsif BUS_RX.addr(6 downto 0) = "0110111" then
       set_output_mult(1) <= BUS_RX.data(7 downto 0);
       set_output_mult(2) <= BUS_RX.data(15 downto 8);
@@ -218,7 +220,7 @@ begin
     elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
       BUS_TX.data                 <= multiplicity_enable(1)(63 downto 32);
     elsif BUS_RX.addr(6 downto 0) = "0110110" then
-      BUS_TX.data                 <= x"000000" & "00" & std_logic_vector(set_stretcher);
+      BUS_TX.data                 <= x"00000" & "000" & set_stretchedge & "00" & std_logic_vector(set_stretcher);
     elsif BUS_RX.addr(6 downto 0) = "0110111" then
       BUS_TX.data <= x"0000" & set_output_mult(2) & set_output_mult(1);
     elsif BUS_RX.addr(6 downto 0) = "0111000" then
@@ -251,7 +253,7 @@ end generate;
 inp_inv           <= INPUT xor invert(INPUTS-1 downto 0);
 inp_long          <= inp_shift(0) or inp_shift(1);
 
-inp_edge          <= not inp_shift(1) and inp_shift(2) when rising_edge(CLK);
+inp_edge          <= inp_shift(1) and not inp_shift(2) when rising_edge(CLK);
 
 ----------------------------
 --  Extended Stretcher
@@ -266,7 +268,7 @@ begin
   gen_long_stretchers : for i in 0 to INPUTS-1 generate
     process begin
       wait until rising_edge(CLK);
-      if inp_shift(1)(i) = '1' then
+      if (inp_shift(1)(i) = '1' and set_stretchedge = '0') or (inp_edge(i) = '1' and set_stretchedge = '1') then
         stretchcnt(i) <= set_stretcher;
         inp_verylong(i) <= '1';
       elsif stretchcnt(i) > 0 then