FREQUENCY PORT CLOCK_CAL 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "med_stat_debug[11]" 200 MHz;
+
FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
BLOCK PATH TO PORT "LED*";
BLOCK PATH FROM PORT "TEMP_LINE";
BLOCK PATH TO PORT "TEST_LINE*";
-MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
-MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
-MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
-MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
-# GSR_NET NET "GSR_N";
+GSR_NET NET "clear_i";
# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+
+
+REGION "MEDIA" "R81C45D" 12 28;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
CLOCK_CAL : in std_logic; --on-board calibration oscillator
INPUT : in std_logic_vector(32 downto 1);
- PWM : out std_logic_vector(32 downto 1);
+-- PWM : out std_logic_vector(32 downto 1);
--Additional IO
SIG : inout std_logic_vector(4 downto 1);
signal hit_in_i : std_logic_vector(32 downto 1);
signal logic_analyser_i : std_logic_vector(16 downto 1);
- signal led_los_lock : std_logic;
- signal los_count : unsigned(23 downto 0);
+-- signal led_los_lock : std_logic;
+-- signal los_count : unsigned(23 downto 0);
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
-- signal c : a_t;
-- attribute syn_keep of c : signal is true;
-- attribute syn_preserve of c : signal is true;
-
+ signal link_stat_in_reg : std_logic;
component usrmclk
DEBUG_OUT => debug_clock_reset
);
- process
- begin
- wait until rising_edge(CLOCK_CAL);
- if debug_clock_reset(0) = '0' then
- led_los_lock <= '0';
- los_count <= (others => '0');
- elsif los_count(23) = '0' then
- los_count <= los_count + 1;
- else
- led_los_lock <= '1';
- end if;
- end process;
+-- process
+-- begin
+-- wait until rising_edge(CLOCK_CAL);
+-- if debug_clock_reset(0) = '0' then
+-- led_los_lock <= '0';
+-- los_count <= (others => '0');
+-- elsif los_count(23) = '0' then
+-- los_count <= los_count + 1;
+-- else
+-- led_los_lock <= '1';
+-- end if;
+-- end process;
---------------------------------------------------------------------------
PWM => pwm_i
);
- PWM <= pwm_i;
+-- PWM <= pwm_i;
end generate;
gen_DAC : if DIRICH_VERSION = 2 generate
---------------------------------------------------------------------------
-- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0);
--- hdr_io(8) <= TEST_LINE(9);
--- TEST_LINE(10) <= hdr_io(9);
+ hdr_io(8) <= TEST_LINE(1);
+ TEST_LINE(2) <= hdr_io(9);
-- TEST_LINE(14 downto 11) <= time_counter(31 downto 28);
--- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0);
+-- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ;
--& med_stat_debug(18 downto 8);
+link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc);
+--TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0);
+--TEST_LINE(8 downto 1) <= clk_sys & med_stat_debug(9) & med_stat_debug(10) & med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg;
+ TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6);
---------------------------------------------------------------------------
-- LCD Data to display
---------------------------------------------------------------------------
LED_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_ORANGE <= debug_clock_reset(0) or led_off;
LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
- LED_YELLOW <= led_los_lock or led_off;
+ LED_YELLOW <= not med2int(0).stat_op(8) or led_off;
-- TDC
-------------------------------------------------------------------------------
- THE_TDC : entity work.TDC_record
- generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
- STATUS_REG_NR => 21, -- Number of status regs
- DEBUG => c_YES,
- SIMULATION => c_NO)
- port map (
- RESET => reset_i,
- CLK_TDC => CLOCK_IN,
- CLK_READOUT => clk_sys, -- Clock for the readout
- REFERENCE_TIME => TRIG_IN, -- Reference time input
- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC
- -- Trigger signals from handler
- BUSRDO_RX => readout_rx,
- BUSRDO_TX => readout_tx(0),
- -- Slow control bus
- BUS_RX => bustdc_rx,
- BUS_TX => bustdc_tx,
- -- Dubug signals
- INFO_IN => timer,
- LOGIC_ANALYSER_OUT => logic_analyser_i
- );
-
--- For single edge measurements
- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
- hit_in_i <= INPUT;
- end generate;
-
--- For ToT Measurements
- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
- Gen_Hit_In_Signals : for i in 1 to 16 generate
- hit_in_i(i*2-1) <= INPUT(i);
- hit_in_i(i*2) <= not INPUT(i);
- end generate Gen_Hit_In_Signals;
- end generate;
-
-
--- readout_tx(0).data_finished <= '1';
--- readout_tx(0).data_write <= '0';
--- readout_tx(0).busy_release <= '1';
+-- THE_TDC : entity work.TDC_record
+-- generic map (
+-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+-- STATUS_REG_NR => 21, -- Number of status regs
+-- DEBUG => c_YES,
+-- SIMULATION => c_NO)
+-- port map (
+-- RESET => reset_i,
+-- CLK_TDC => CLOCK_IN,
+-- CLK_READOUT => clk_sys, -- Clock for the readout
+-- REFERENCE_TIME => TRIG_IN, -- Reference time input
+-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+-- HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC
+-- -- Trigger signals from handler
+-- BUSRDO_RX => readout_rx,
+-- BUSRDO_TX => readout_tx(0),
+-- -- Slow control bus
+-- BUS_RX => bustdc_rx,
+-- BUS_TX => bustdc_tx,
+-- -- Dubug signals
+-- INFO_IN => timer,
+-- LOGIC_ANALYSER_OUT => logic_analyser_i
+-- );
+--
+-- -- For single edge measurements
+-- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+-- hit_in_i <= INPUT;
+-- end generate;
+--
+-- -- For ToT Measurements
+-- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+-- Gen_Hit_In_Signals : for i in 1 to 16 generate
+-- hit_in_i(i*2-1) <= INPUT(i);
+-- hit_in_i(i*2) <= not INPUT(i);
+-- end generate Gen_Hit_In_Signals;
+-- end generate;
+
+
+readout_tx(0).data_finished <= '1';
+readout_tx(0).data_write <= '0';
+readout_tx(0).busy_release <= '1';
end architecture;
jspc29 / dirich.git / commitdiff