adding latest changes to compile script and trb3sc_tools

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 88b78f2ec146d8e680dcc7822ea662930679e199..05ae113a4cc49ad9735e5c538576e6b3ada39c9f 100644 (file)
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -249,9 +249,14 @@ end generate;
     ADC_CS  <= spi_cs(7);
     ADC_MOSI <= spi_sdo;
     
-    
+    busspi_tx.unknown <= '0';    
   end generate;
-  busspi_tx.unknown <= '0';
+
+   gen_no_uart : if INCLUDE_SPI = 0 generate
+     busspi_tx.unknown <= busspi_rx.write or busspi_rx.read;
+     busspi_tx.ack <= '0'; busspi_tx.nack <= '0';
+     busspi_tx.data <= (others => '0');
+   end generate;
 
 ---------------------------------------------------------------------------
 -- UART
@@ -270,6 +275,11 @@ end generate;
         BUS_TX    => busuart_tx
         );
   end generate;      
+   gen_no_uart : if INCLUDE_UART = 0 generate
+     busuart_tx.unknown <= busuart_rx.write or busuart_rx.read;
+     busuart_tx.ack <= '0'; busuart_tx.nack <= '0';
+     busuart_tx.data <= (others => '0');
+   end generate;
 
 ---------------------------------------------------------------------------
 -- Debug Connection
@@ -305,7 +315,7 @@ end generate;
 -- Trigger logic
 ---------------------------------------------------------------------------
 gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
-  THE_TRIG_LOGIC : input_to_trigger_logic
+  THE_TRIG_LOGIC : entity work.input_to_trigger_logic_record
     generic map(
       INPUTS    => TRIG_GEN_INPUT_NUM,
       OUTPUTS   => TRIG_GEN_OUTPUT_NUM
@@ -316,19 +326,16 @@ gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
       INPUT     => TRIG_GEN_INPUTS,
       OUTPUT    => TRIG_GEN_OUTPUTS,
 
-      DATA_IN   => bustrig_rx.data,  
-      DATA_OUT  => bustrig_tx.data, 
-      WRITE_IN  => bustrig_rx.write,
-      READ_IN   => bustrig_rx.read,
-      ACK_OUT   => bustrig_tx.ack,  
-      NACK_OUT  => bustrig_tx.nack, 
-      ADDR_IN   => bustrig_rx.addr
+      BUS_RX    => bustrig_rx,
+      BUS_TX    => bustrig_tx
       );      
 
 end generate;
 
 gen_noTRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
-  bustrig_tx.unknown <= bustrig_rx.read or bustrig_rx.write;
+     bustrig_tx.unknown <= bustrig_rx.write or bustrig_rx.read;
+     bustrig_tx.ack <= '0'; bustrig_tx.nack <= '0';
+     bustrig_tx.data <= (others => '0');
 end generate;
 
 ---------------------------------------------------------------------------
@@ -354,10 +361,13 @@ gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
       NACK_OUT  => busmon_tx.nack, 
       ADDR_IN   => busmon_rx.addr
       );
+  busmon_tx.unknown <= '0';    
 end generate;
 
 gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate
-  busmon_tx.unknown <= busmon_rx.read or busmon_rx.write;
+     busmon_tx.unknown <= busmon_rx.write or busmon_rx.read;
+     busmon_tx.ack <= '0'; busmon_tx.nack <= '0';
+     busmon_tx.data <= (others => '0');
 end generate;
 
 ---------------------------------------------------------------------------
@@ -390,7 +400,7 @@ gen_nolcdio : if INCLUDE_LCD = 0 generate
   HEADER_IO(3)  <= spi_sdo;
   -- HEADER_IO(4)  <= ;
   HEADER_IO(5)  <= spi_sck;
-  HEADER_IO(6)  <= spi_cs;
+  HEADER_IO(6)  <= spi_cs(8);
 end generate;
 
 

diff --git a/scripts/compile.pl b/scripts/compile.pl
index e33a69fd0dca9e7e02467423956b6a5d0ce6d6ed..ada91d17c07ac24c226f4a829a8f4fa04f20d974 100755 (executable)
--- a/scripts/compile.pl
+++ b/scripts/compile.pl
@@ -405,7 +405,7 @@ if($bitgen==1 || $all==1){
     print GREEN, "Generating bit file...\n\n", RESET;
 
     $c=qq|ltxt2ptxt $TOPNAME.ncd|;
-    execute($c);
+    execute($c) unless $config{no_ltxt2ptxt} ;
 
     $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
     execute($c);

diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd
index 18d96affc9976d67569083c828fad9421739de92..4ee78d9fe6f0f52d5ea86add71fdd5ceabcf312a 100644 (file)
--- a/tdctemplate/config.vhd
+++ b/tdctemplate/config.vhd
@@ -12,7 +12,7 @@ package config is
 
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 2;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 41;  -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
@@ -46,9 +46,9 @@ package config is
     --input monitor and trigger generation logic
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_YES;
     constant INCLUDE_STATISTICS     : integer  := c_YES;
-    constant TRIG_GEN_INPUT_NUM     : integer  := 20;
+    constant TRIG_GEN_INPUT_NUM     : integer  := 40;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 4;
-    constant MONITOR_INPUT_NUM      : integer  := 24;    
+    constant MONITOR_INPUT_NUM      : integer  := 44;    
    
 ------------------------------------------------------------------------------
 --End of design configuration

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 15af9181c87245f25e990450043ac2b11687007d..3cdfea376db5f38bff3df7ad0c4114c6793c087b 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -117,7 +117,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 
 #SlowControl files

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index e2e16ebb8b7f75365c1f97387e5e231ddd13ac76..cb7e4769ac3fee8ffb8e4a96d5868d4ec96ca11f 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -351,9 +351,9 @@ begin
       ADC_MISO      => ADC_DOUT,
       ADC_CLK       => ADC_CLK,
       --Trigger & Monitor 
-      MONITOR_INPUTS(19 downto 0) => KEL(20 downto 1),
-      MONITOR_INPUTS(23 downto 20) => trig_gen_out_i,
-      TRIG_GEN_INPUTS  => KEL(20 downto 1),
+      MONITOR_INPUTS(39 downto 0) => KEL(40 downto 1),
+      MONITOR_INPUTS(43 downto 40) => trig_gen_out_i,
+      TRIG_GEN_INPUTS  => KEL(40 downto 1),
       TRIG_GEN_OUTPUTS => trig_gen_out_i,
       --SED
       SED_ERROR_OUT => sed_error_i,

diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj
index 1ae35c241023c31857a089e32c94f9ac6d6636b3..fa52f08ebb880dec1ae72b01c5596dfc6a0e5421 100644 (file)
--- a/template/trb3sc_basic.prj
+++ b/template/trb3sc_basic.prj
@@ -115,7 +115,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 
 #SlowControl files