}
my->currAddr = 0xffffffff; /* start at the end */
my->bankRequested = 1; /* of the empty bank */
- my->pipeFull = 1;
- my->daqRq = 0;
- my->daqGr = 2;
- my->fifo = 0x01000000;
+ my->pipeFull = 2;
+ my->daqRq = 1;
+ my->daqGr = 13;
+ my->fifo = LVL2_PIPE2_BASE;
return 0;
}
void HwTip_requestBuffer(HwTip *my) {
LVme_clrBitL(my->lvme, EXT_DAQ, my->daqRq);
- while (LVme_tstBitL(my->lvme, EXT_DAQ, my->daqGr)) {
+ while (LVme_tstBitL(my->lvme, EXT_STATUS, my->daqGr)) {
#if 1
struct timespec tS, *t = &tS;
t->tv_sec = 0;
my->bankRequested = 1;
my->pipeFull = 2;
my->daqRq = 1;
- my->daqGr = 3;
- my->fifo = 0x01000800;
+ my->daqGr = 13;
+ my->fifo = LVL2_PIPE2_BASE;
} else {
my->bankRequested = 0;
my->pipeFull = 1;
my->daqRq = 0;
- my->daqGr = 2;
- my->fifo = 0x01000000;
+ my->daqGr = 12;
+ my->fifo =LVL2_PIPE1_BASE;
}
msglog(LOG_DEBUG, "wait for data\n");
while (!LVme_tstBitL(my->lvme, EXT_STATUS, my->pipeFull)) {
msglog(LOG_DEBUG, "data available\n");
LVme_setBitL(my->lvme, EXT_DAQ, my->daqRq);
- my->currAddr = my->fifo + 0x4;
+ my->currAddr = my->fifo + 0x8;
}
int HwTip_isBusy(HwTip *my) {
- return !LVme_tstBitL(my->lvme, EXT_DAQ, my->daqGr);
+ return !LVme_tstBitL(my->lvme, EXT_STATUS, my->daqGr);
}
int HwTip_isEmpty(HwTip *my) {
size_t size;
UInt1 trigTag;
-#if 0
+#if 1
size = LVme_getL(my->lvme, my->currAddr);
/* copy one sub evt from RC to memory */
/**** Headerfile for TOF-RTU registers */
/**** E.Lins 13-Jan-2000 */
+/* $Id: tof_defs.h,v 1.2 2000-05-09 13:36:08 hades Exp $ */
+/* $Source: /misc/hadesprojects/daq/cvsroot/eventbuilder/hadaq/Attic/tof_defs.h,v $ */
+
/* Onboard components base addresses... */
#define SHARC5BASE 0x00800000
#define SHARC6BASE 0x00a00000
+#define LVL2_PIPE1_BASE 0x01000000
+#define LVL2_PIPE2_BASE 0x01008000
/* registers in external memory */
#define LVL2_DAQ1_BSY 0x00000100U
#define LVL2_DAQ2_BSY 0x00000200U
+#define LVL2_DAQ1_GR 0x00001000U
+#define LVL2_DAQ2_GR 0x00002000U
+
/* bits in the daq register */
#define LVL2_DAQ1_RQ 0x00000001U
#define LVL2_DAQ2_RQ 0x00000002U
-#define LVL2_DAQ1_GR 0x00000004U
-#define LVL2_DAQ2_GR 0x00000008U
/* TUNDRA internal registers */