\begin{description*}
\item[Central FPGA]~
\begin{description*}
- \item[c000] contains a CTS
- \item[c001] contains a CTS, use with AddOn for trigger signals
+ \item[cXX0] contains a CTS
+ \item[cXX1] contains a CTS, use with AddOn for trigger signals
+ \item[8XXX] uses RX clock as main internal clock
\item[0e00] contains a GbE link for slow control and read-out
\item[0d00] contains a GbE link for read-out only
\item[0010] accepts triggers from optical link SFP1
\item[2XXX] use with multipurpose test AddOn
\item[3XXX] use with SFP hub AddOn
\item[4XXX] use with Wasa adapter AddOn
+ \item[8XXX] uses RX clock as main internal clock
\item[X0nX] contains $2^n$ TDC channels, single edge
\item[X1nX] contains $2^n$ TDC channels, double edge
\item[X2XX] contains a network hub
\begin{itemize*}
\item 0xF300 for the central FPGA
\item 0xF305 for the peripheral FPGA
- \item 0xF301 for a design for FPGA 1 only
- \item 0xF302 for a design for FPGA 2 only
- \item 0xF303 for a design for FPGA 3 only
- \item 0xF304 for a design for FPGA 4 only
+ \item 0xF30n for a design for FPGA n only
+ \item 0xF3C0 default for a design with CTS
\end{itemize*}
\input{CtsSlowControl}
\cleardoublepage
+ \section{Media Interfaces}
+ \input{MediaInterfaces}
\part{Experimental Setups and Configurations}
\section{Trigger Time vs Reference Time}